Rev. 1.11 - UBiio

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Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM Symbol Parameter Description Units t ERR.nPER t CH.AVG Cumulative error across n cycles Average high-pulse width t ERR.2PER is defined as the cumulative error across n consecutive cycles ps from t CK.AVG : ⎛i+ n– 1 ⎞ tERR( nper) = ⎜ tCK ⎟ (3) ∑ j – n × tCK( avg) ⎜ ⎟ ⎝ j = i ⎠ where, i = 1 to 200 and n=3 for t ERR.3PER n = 4 for t ERR.4PER n = 5 for t ERR.5PER 6 ≤ n ≤ 10 for t ERR.6-10PER 11 ≤ n ≤ 50 for t ERR.11-50PER t CH.AVG is defined as the average high-pulse width, as calculated across any consecutive 200 high pulses: t CK.AVG tCH( avg) = ⎛ ⎞ 1 ( ---------------------------------------- N× tCK( avg) ) . ⎜ ⎜∑ tCH ⎟ j ⎟ ⎝ ⎠ N j = 1 (4) N=200 t CL.AVG Average low-pulse width t CL.AVG is defined as the average low-pulse width, as calculated across any consecutive 200 low pulses: t CK.AVG tCL( avg) = ⎛ ⎞ 1 ( --------------------------------------- N× tCK( avg) ) . ⎜ ⎜∑ tCL ⎟ j ⎟ ⎝ ⎠ N j = 1 (5) N=200 t JIT.DUTY Duty-cycle jitter t JIT.DUTY = Min/Max of {t JIT.CH , t JIT.CL }, where: t JIT.CH is the largest deviation of any single t CH from t CH.AVG t JIT.CL is the largest deviation of any single t CL from t CL.AVG t JIT.CH = {t CHi - t CH.AVG × t CK.AVG } where i=1 to 200 t JIT.CL = {t CLi - t CL.AVG × t CK.AVG } where i=1 to 200 ps The following parameters are specified per their average values however, it is understood that the following relationship between the average timing and the absolute instantaneous timing holds all the time. Rev. 1.11, 2007-07 60 11172006-LBIU-F1TN
Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM TABLE 57 Absolute Jitter Value Definitions Symbol Parameter Min. Max. Unit t CK.ABS Clock period t CK.AVG(Min) + t JIT.PER(Min) t CK.AVG(Max) + t JIT.PER(Max) ps t CH.ABS Clock high-pulse width t CH.AVG(Min) x t CK.AVG(Min) + t JIT.DUTY(Min) t CH.AVG(Max) x t CK.AVG(Max) + t JIT.DUTY(Max) t CL.ABS Clock low-pulse width t CL.AVG(Min) x t CK.AVG(Min) + t JIT.DUTY(Min) t CL.AVG(Max) x t CK.AVG(Max) + t JIT.DUTY(Max) Example: for DDR2-667, t CH.ABS.MIN = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps. ps ps Table 58 shows clock-jitter specifications. TABLE 58 Clock-Jitter Specifications for –667 and –800 Symbol Parameter DDR2 -667 DDR2 -800 Unit Min. Max. Min. Max. t CK.AVG Average clock period nominal w/o jitter 3000 8000 2500 8000 ps t JIT.PER Clock-period jitter –125 +125 –100 +100 ps t JIT(PER,LCK) Clock-period jitter during DLL locking period –100 +100 –80 +80 ps t JIT.CC Cycle-to-cycle clock-period jitter –250 +250 –200 +200 ps t JIT(CC,LCK) Cycle-to-cycle clock-period jitter during DLLlocking period –200 +200 –160 +160 ps t ERR.2PER Cumulative error across 2 cycles –175 +175 –150 +150 ps t ERR.3PER Cumulative error across 3 cycles –225 +225 –175 +175 ps t ERR.4PER Cumulative error across 4 cycles –250 +250 –200 +200 ps t ERR.5PER Cumulative error across 5 cycles –250 +250 –200 +200 ps t ERR(6-10PER) Cumulative error across n cycles with n = 6 .. 10, inclusive t ERR(11-50PER) Cumulative error across n cycles with n = 11 .. 50, inclusive –350 +350 –300 +300 ps –450 +450 –450 +450 ps t CH.AVG Average high-pulse width 0.48 0.52 0.48 0.52 t CK.AVG t CL.AVG Average low-pulse width 0.48 0.52 0.48 0.52 t CK.AVG t JIT.DUTY Duty-cycle jitter –125 +125 –100 +100 ps Rev. 1.11, 2007-07 61 11172006-LBIU-F1TN
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July 2007 HY[B/I]18T256400B[C/F](L)
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Internet Data Sheet HY[B/I]18T256[4
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Rev. 1.11 - UBiio

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