Rev. 1.11 - UBiio

Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t JIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t JIT.DUTY.MIN = – 72 ps
and t JIT.DUTY.MAX = + 93 ps, then t RPST.MIN(DERATED) = t RPST.MIN + t JIT.DUTY.MIN = 0.4 x t CK.AVG – 72 ps = + 928 ps and t RPST.MAX(DERATED) = t RPST.MAX
+ t JIT.DUTY.MAX = 0.6 x t CK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support t nPARAM = RU{t PARAM / t CK.AVG }, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t nRP = RU{t RP / t CK.AVG }, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t RP = 15 ns, the device will support
t nRP = RU{t RP / t CK.AVG } = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
35) t WTR is at lease two clocks (2 x t CK ) independent of operation frequency.
Rev. 1.11, 2007-07 52
11172006-LBIU-F1TN