Rev. 1.11 - UBiio

Internet Data Sheet
3 Functional Description
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
This chapter contains the functional description.
Field Bits Type 1) Description
TABLE 18
Mode Register Definition (BA[2:0] = 000 B )
BA2 16 reg. addr. Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0 B BA2 Bank Address
BA1 15 Bank Address [1]
0 B BA1 Bank Address
BA0 14 Bank Address [0]
0 B BA0 Bank Address
A13 13 Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0 B A13 Address bit 13
PD 12 w Active Power-Down Mode Select
0 B PD Fast exit
1 B PD Slow exit
WR [11:9] w Write Recovery 2)
Note: All other bit combinations are illegal.
001 B WR 2
010 B WR 3
011 B WR 4
100 B WR 5
101 B WR 6
DLL 8 w DLL Reset
0 B DLL No
1 B DLL Yes
TM 7 w Test Mode
0 B TM Normal Mode
1 B TM Vendor specific test mode
Rev. 1.11, 2007-07 21
11172006-LBIU-F1TN