Rev. 1.11 - UBiio

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Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM TABLE 54 DRAM Component Timing Parameter by Speed Grade - DDR2–533 Parameter Symbol DDR2–533 Unit Notes 1)2)3)4)5) DQ output access time from CK / CK t AC –500 +500 ps CAS A to CAS B command period t CCD 2 — t CK CK, CK high-level width t CH 0.45 0.55 t CK CKE minimum high and low pulse width t CKE 3 — t CK CK, CK low-level width t CL 0.45 0.55 t CK Auto-Precharge write recovery + precharge t DAL WR + t RP — t CK 7)17) time Minimum time clocks remain ON after CKE t DELAY t IS + t CK + t IH –– ns 8) asynchronously drops LOW DQ and DM input hold time (differential data t DH (base) 225 –– ps 9) strobe) DQ and DM input hold time (single ended data t DH1 (base) –25 — ps 10) strobe) DQ and DM input pulse width (each input) t DIPW 0.35 — t CK DQS output access time from CK / CK t DQSCK –450 +450 ps Min. Max. 6) DQS input low (high) pulse width (write cycle) t DQSL,H 0.35 — t CK DQS-DQ skew (for DQS & associated DQ t DQSQ — 300 ps signals) 10) Write command to 1st DQS latching transition t DQSS – 0.25 + 0.25 t CK DQ and DM input setup time (differential data t DS (base) 100 — ps 10) strobe) DQ and DM input setup time (single ended data t DS1 (base) –25 — ps 10) strobe) DQS falling edge hold time from CK (write t DSH 0.2 — t CK cycle) DQS falling edge to CK setup time (write cycle) t DSS 0.2 — t CK Clock half period t HP MIN. (t CL, t CH ) 11) Data-out high-impedance time from CK / CK t HZ — t AC.MAX ps 12) Address and control input hold time t IH (base) 375 — ps 10) Address and control input pulse width t IPW 0.6 — t CK (each input) Address and control input setup time t IS (base) 250 — ps 10) DQ low-impedance time from CK / CK t LZ(DQ) 2 × t AC.MIN t AC.MAX ps 13) DQS low-impedance from CK / CK t LZ(DQS) t AC.MIN t AC.MAX ps 13) MRS command to ODT update delay t MOD 0 12 ns Mode register set command cycle time t MRD 2 — t CK OCD drive mode output delay t OIT 0 12 ns Data output hold time from DQS t QH t HP –t QHS — Data hold skew factor t QHS — 400 ps Rev. 1.11, 2007-07 54 11172006-LBIU-F1TN
Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM Parameter Symbol DDR2–533 Unit Notes 1)2)3)4)5) Average periodic refresh Interval t REFI — 7.8 μs Average periodic refresh Interval t REFI — 3.9 μs 15)17) Auto-Refresh to Active/Auto-Refresh t RFC 75 — ns 16) command period Precharge-All (4 banks) command period t RP t RP — ns Read preamble t RPRE 0.9 1.1 t CK 13) Read postamble t RPST 0.40 0.60 t CK 13) Active bank A to Active bank B command t RRD 7.5 — ns 13)17) period Active bank A to Active bank B command t RRD 10 — ns 15)21) period Internal Read to Precharge command delay t RTP 7.5 — ns Write preamble t WPRE 0.25 — t CK Write postamble t WPST 0.40 0.60 t CK 18) Write recovery time for write without Auto- t WR 15 — ns Precharge Internal Write to Read command delay t WTR 7.5 — ns 19) Exit power down to any valid command t XARD 2 — t CK 20) (other than NOP or Deselect) Exit active power-down mode to Read t XARDS 6 – AL — t CK 20) command (slow exit, lower power) Exit precharge power-down to any valid t XP 2 — t CK command (other than NOP or Deselect) Exit Self-Refresh to non-Read command t XSNR t RFC +10 — ns Exit Self-Refresh to Read command t XSRD 200 — t CK Write recovery time for write with Auto- Precharge WR t WR /t CK t CK 21) 1) V DDQ = 1.8 V ± 0.1 V; V DD = 1.8 V ±0.1 V. 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8 of this datasheet. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS, RDQS / RDQS is defined in Chapter 8.3 of this datasheet. 5) Inputs are not recognized as valid until V REF stabilizes. During the period before V REF stabilizes, CKE = 0.2 x V DDQ is recognized as low. 6) The output timing reference voltage level is V TT . See Chapter 8 for the reference load for timing measurements. 7) For each of the terms, if not already an integer, round to the next highest integer. t CK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) For timing definition, refer to the Component data sheet. 10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 11) MIN (t CL , t CH ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH ). Min. Max. 6) 13)14) Rev. 1.11, 2007-07 55 11172006-LBIU-F1TN
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July 2007 HY[B/I]18T256400B[C/F](L)
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Page 63 and 64: Internet Data Sheet 8 Package Dimen
Page 65 and 66: Internet Data Sheet 9 Product Nomen
Page 71: Internet Data Sheet Edition 2007-07
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Rev. 1.11 - UBiio

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