EECC756 - Shaaban

Cache Coherence Problem ExampleFromP 1$P 2 main memory P 3u = ?u = ?4 $ 5$u:5u:5u = 73Write BackCaches Assumed1u:5Memory2I/O devices1 P1 reads u=5 from memory2 P3 reads u=5 from memory3 P3 writes u=7 to local P3 cache4 P1 reads old u=5 from local P1 cache5 P2 reads old u=5 from memory– Processors see different values for u after event 3.– With write back caches, a value updated in cache may not havebeen written back to memory:• Processes even accessing main memory may see very stale value.– Unacceptable: leads to incorrect program execution.PCA page 274Write by P3not visible to P1, P2EECC756 - Shaaban#12 lec # 10 Spring2013 4-30-2013Time