EECC756 - Shaaban

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Modified Exclusive Shared InvalidSolution:MESI (4-state) Invalidation Protocol• Problem with MSI protocol:– Reading and modifying data is 2 bus transactions, even if not sharing:• e.g. even in sequential program.• BusRd ( I-> S ) followed by BusRdX ( S -> M ).• Add exclusive state (E): Write locally without a bus transaction, but notmodified:– Main memory is up to date, so cache is not necessarily the owner.New “shared” bussignal needed– Four States:• Invalid (I).• Exclusive or exclusive-clean (E): Only this cache has a copy, butnot modified; main memory has same copy.• Shared (S): Two or more caches may have copies.• Modified (M): Dirty.– I -> E on PrRd if no one else has copy. i.e. shared signal, S = 0• Needs “shared” signal S on bus: wired-or line asserted in responseto BusRd.S = 0 Not SharedS = 1 Sharedi.e no other cachehas a copyEECC756 - Shaaban#32 lec # 10 Spring2013 4-30-2013
MESI State Transition DiagramFour States:M = Modified or DirtyE = ExclusiveS = SharedI = InvalidPrWr/BusRdXPrWr/BusRdXPrWr/—MEPrRd/—PrRdPrWr/—BusRd/FlushBusRd/FlushBusRdX/FlushBusRdX/FlushInvalidate / ForcedWrite BackSBusRdX/Flush′S = shared signal= 0 not shared= 1 sharedNot SharedPrRd/BusRd (S)PrRd/—BusRd/Flush′PrRd/BusRd(S)IShared– BusRd(S) Means shared line asserted on BusRd transaction.– Flush: If cache-to-cache sharing, only one cache flushes data.EECC756 - Shaaban#33 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31: ThreeStates:Basic MSI Write-Back In
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

EECC756 - Shaaban

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