EECC756 - Shaaban

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ThreeStates:Basic Write-invalidate invalidate Bus-Snooping Protocol:For Write-Back Caches• Corresponds to ownership protocol. i.e which processor owns the block• Valid state in write-through protocol is divided into two states (3 states total):RW (read-write): (this processor i owns block) or Modified M• The only cache copy existing in the system; owned by the local processor.• Read (R(i)) and (W(i)) can be safely performed in this state.RO (read-only): or Shared S• Multiple cache block copies exist in the system; owned by memory.• Reads ((R(i)), ((R(j)) can safely be performed in this state.INV (invalid): I• Entered when : Not in cache or,– A remote processor writes (W(j) to its cache copy.– A local processor replaces (Z(i) its own copy.• A cache block is uniquely owned after a local write W(i)• Before a block is modified, ownership for exclusive access is obtained by a readonlybus transaction broadcast to all caches and memory.• If a modified remote block copy exists, memory is updated (forced write back),local copy is invalidated and ownership transferred to requesting cache.i = Local Processorj = Other (remote) processorFor a cache block in local processor iEECC756 - Shaaban#28 lec # 10 Spring2013 4-30-2013
Write-invalidate Bus-Snooping ProtocolFor Write-Back CachesState Transition DiagramFor a cache block in local processor iR(i)W(i)Z(j)RW(Processor iowns block)i local processorj other processorW(i)W(j)Z(i)R(j)W(i)INVForce write backR(i)ROOwned bymemoryW(j), Z(i)RW: Read-WriteRO: Read OnlyINV: Invalidated ornot in cacheR(i)R(j)Z(j)Other processor writesinvalidateW(i) = Write to block by processor iW(j) = Write to block copy in cache j by processor j ≠ iR(i) = Read block by processor i.R(j) = Read block copy in cache j by processor j ≠ iZ(i) = Replace block in cache .Z(j) = Replace block copy in cache j ≠ iR(j), Z(j), W(j), Z(i)EECC756 - Shaaban#29 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27: Problems With Write-Through• High
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

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