EECC756 - Shaaban

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PrRd/—A read bythis processorA read bythis processorPrRd/BusRdA write by otherprocessor to blocki.e W(j)PrWr/BusWrWrite-invalidate invalidate Bus-Snooping Protocoli.e R(i)VIPrWr/BusWrA write bythis processori.e W(j)BusWr/—Snooper sensesa write by other processorto same block -> invalidateFor Write-Through CachesAlternate State Transition DiagramProcessor-initiated transactionsBus-snooper-initiated transactionsV = ValidI = InvalidA/B means if A is observed B is generated.Processor Side Requests:read (PrRd)write (PrWr)Bus Side or snooper/cache controller Actions:bus read (BusRd)bus write (BusWr)– Two states per block in each cache, as in uniprocessor.• state of a block can be seen as p-vector (for all p processors). p bits– Hardware state bits associated with only blocks that are in the cache.• other blocks can be seen as being in invalid (not-present) state in that cache– Write will invalidate all other caches (no local change of state).• can have multiple simultaneous readers of block,but write invalidates them.PCA page 281i.e W(i)EECC756 - Shaaban#26 lec # 10 Spring2013 4-30-2013
Problems With Write-Through• High bandwidth requirements:– Every write from every processor goes to shared bus and memory.– Consider 200MHz, 1 CPI processor, and 15% of the instructionsare 8-byte stores.– Each processor generates 30M stores or 240MB data per second.– 1GB/s bus can support only about 4 processors without saturating.– Write-through especially is unpopular for SMPs.• Write-back caches absorb most writes as cache hits:– Write hits don’t go on bus. Visible to all– But now how do we ensure write propagation and serialization?• Requires more sophisticated coherence protocols.In correct orderi.e write atomicityPCA page 283EECC756 - Shaaban#27 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25: Write-invalidate invalidate Bus-Sno
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

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