EECC756 - Shaaban

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TwoStates:IInvalidationActionWrite-invalidate invalidate Bus-Snooping Protocol:For Write-Through CachesThe state of a cache block copy of local processor i cantake one of two states (j represents a remote processor):Valid State:V• All processors can read (R(i), R(j)) safely.• Local processor i can also write W(i)• In this state after a successful read R(i) or write W(i)Invalid State:not in cache or,• Block being invalidated.• Block being replaced Z(i) or Z(j)• When a remote processor writes W(j) to its cache copy, allother cache copies become invalidated. V I– Bus write cycles are higher than bus read cycles due torequest invalidations to remote caches.Assuming write allocatei = Local Processorj = Other (remote) processorEECC756 - Shaaban#24 lec # 10 Spring2013 4-30-2013
Write-invalidate invalidate Bus-Snooping ProtocolR(j)Z(j)Z(i)W(j)For Write-Through CachesState Transition DiagramInvalidIR(i), W(i)W(j), Z(i)ValidVW(i) = Write to block by processor iW(j) = Write to block copy in cache j by processor j ≠ iR(i) = Read block by processor i.R(j) = Read block copy in cache j by processor j ≠ iZ(i) = Replace block in cache .Z(j) = Replace block copy in cache j ≠ ii local processor j other processorLocal writeAssuming writeallocate usedFor a cache blockin local processor iR(i)W(i)R(j)Z(j)Write by other processor j, invalidateEECC756 - Shaaban#25 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23: Coherence with Write-through throug
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

EECC756 - Shaaban

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