EECC756 - Shaaban

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Uniform Memory Access (UMA) Multiprocessors• Bus-basedMultiprocessors: (SMPs)– A number of processors (commonly 2-4) 2in a single node share physical memory viasystem bus or point-toto-point interconnects (e.g. AMD64 via. HyperTransport)– Symmetric access to all of main memory from any processor.• Commonly called: Symmetric Memory Multiprocessors (SMPs).– Building blocks for larger parallel systems (MPPs, clusters)– Also attractive for high throughput servers– Bus-snooping mechanisms used to address the cache coherency problem.• Shared cache Multiprocessor Systems:– Low-latency sharing and prefetching across processors.– Sharing of working sets.– No cache coherence problem (and hence no false sharing either).– But high bandwidth needs and negative interference (e.g. conflicts).– Hit and miss latency increased due to intervening switch and cache size.– Used in mid 80s to connect a few of processors on a board (Encore, Sequent).– Used currently in chip multiprocessors (CMPs): 2-4 processors on a single chip.e.g IBM Power 4, 5: two processor cores on a chip (shared L2).• Dancehall:– No local memory associated with a node.– Not a popular design: All memory is uniformly costly to access over the network for allprocessors.EECC756 - Shaaban#6 lec # 10 Spring2013 4-30-2013
Uniform Memory Access Example:Intel Pentium Pro QuadCPUInterruptcontrollerBus interface256-KBL 2 $P-PromoduleP-PromoduleCirca 1997P-PromoduleSharedFSBP-Pro bus (64-bit data, 36-bit addr ess, 66 MHz)PCIbridgePCIbridgeMemorycontrollerPCII/OcardsPCI busPCI busMIU1-, 2-, or 4-wayinterleavedDRAMBus-Based Symmetric Memory Processors (SMPs).A single Front Side Bus (FSB) is shared among processorsThis severely limits scalability to only 2-4 processors• All coherence and multiprocessingglue in processor module• Highly integrated, targeted at highvolumeRepeated here from lecture 1EECC756 - Shaaban#7 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5: Shared Memory Multiprocessors Varia
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

EECC756 - Shaaban

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