EECC756 - Shaaban

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Cache Coherence Approaches• Bus-Snooping Protocols: Used in bus-based systems where allprocessors observe memory transactions and take proper action toinvalidate or update local cache content if needed.• Directory Schemes: Used in scalable cache-coherent distributedmemorymultiprocessor systems where cache directories are used tokeep a record on where copies of cache blocks reside.• Shared Caches:– No private caches.Not Scalable– This limits system scalability (limited to chip multiprocessors, CMPs).• Non-cacheable Data:– Not to cache shared writable data:• Locks, process queues.• Data structures protected by critical sections.– Only instructions or private data is cacheable.– Data is tagged by the compiler.• Cache Flushing:– Flush cache whenever a synchronization primitive is executed.– Slow unless special hardware is used.ScalableNot ScalableEECC756 - Shaaban#18 lec # 10 Spring2013 4-30-2013
Cache Coherence Using A Bus• Built on top of two fundamentals of uniprocessor systems:i.e .SMPs1 Bus transactions.2 State transition diagram of cache blocks.• Uniprocessor bus transaction:– Three phases: arbitration, command/address, data transfer.– All devices observe addresses, one is responsible for transaction• Uniprocessor cache block states:– Effectively, every block is a finite state machine.– Write-through, write no-allocate has two states:valid, invalid.– Write-back caches have one more state: Modified (“dirty”).• Multiprocessors extend both these two fundamentalssomewhat to implement cache coherence using a bus.PCA page 274Three States: Valid (V), Invalid (I), Modified (M)EECC756 - Shaaban#19 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17: Write Atomicity• Write Atomicity:
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

EECC756 - Shaaban

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