EECC756 - Shaaban

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Cache Coherence Problem ExampleFromP 1$P 2 main memory P 3u = ?u = ?4 $ 5$u:5u:5u = 73Write BackCaches Assumed1u:5Memory2I/O devices1 P1 reads u=5 from memory2 P3 reads u=5 from memory3 P3 writes u=7 to local P3 cache4 P1 reads old u=5 from local P1 cache5 P2 reads old u=5 from memory– Processors see different values for u after event 3.– With write back caches, a value updated in cache may not havebeen written back to memory:• Processes even accessing main memory may see very stale value.– Unacceptable: leads to incorrect program execution.PCA page 274Write by P3not visible to P1, P2EECC756 - Shaaban#12 lec # 10 Spring2013 4-30-2013Time
A Coherent Memory System: IntuitionReading a memory location should return the latest valuewritten (by any process).• Easy to achieve in uniprocessors:– Except for DMA-based I/O: Coherence between DMA I/O devices andprocessors.– Infrequent so software solutions work:• Uncacheable memory regions, uncacheable operations, flush pages,pass I/O data through caches.• The same should hold when processes run on different processors:– e.g. Results should be the same as if the processes were interleaved (orrunning) on a uniprocessor.• Coherence problem much more critical in multiprocessors:– Pervasive.– Performance-critical.– Must be treated as a basic hardware design issue.PCA page 275EECC756 - Shaaban#13 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11: Cache Coherence in Shared MemoryMul
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

EECC756 - Shaaban

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