EECC756 - Shaaban

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Basic DefinitionsExtend definitions in uniprocessors to multiprocessors:• Memory operation: a single read (load), write (store) or read-modifywriteaccess to a memory location.– Assumed to execute atomically: 1- (visible) with respect to (w.r.t) eachother and 2- in the same order.• Issue: A memory operation issues when it leaves processor’s internalenvironment and is presented to memory system (cache, buffer …).• Perform: operation appears to have taken place, as far as processorcan tell from other memory operations it issues.– A write performs w.r.t. the processor when a subsequent read by theprocessor returns the value of that write or a later write (no RAW,WAW).– A read perform w.r.t the processor when subsequent writes issued bythe processor cannot affect the value returned by the read (no WAR).• In multiprocessors, stay same but replace “the” by “a” processor– Also, complete: perform with respect to all processors.– Still need to make sense of order in operations from different processes.PCA page 276EECC756 - Shaaban#14 lec # 10 Spring2013 4-30-2013
Shared Memory Access Consistency• A load by processor P i is performed with respect toprocessor P k at a point in time when the issuing of asubsequent store to the same location by P k cannot affectthe value returned by the load (no WAW, WAR).• A store by P i is considered performed with respect to P kat one time when a subsequent load from the sameaddress by P k returns the value by this store (no RAW).• A load is globally performed (i.e. complete) if it isperformed with respect to all processors and if the storethat is the source of the returned value has beenperformed with respect to all processors.EECC756 - Shaaban#15 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13: A Coherent Memory System: Intuition
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

EECC756 - Shaaban

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