EECC756 - Shaaban

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Formal Definition of Coherence• Results of a program: values returned by its read (load) operations• A memory system is coherent if the results of any execution of aprogram are such that for each location, it is possible to constructa hypothetical serial order of all operations to the location that isconsistent with the results of the execution and in which:1. operations issued by any particular process occur in the orderissued by that process, and2. the value returned by a read is the value written by the latest writeto that location in the serial order• Two necessary conditions:– Write propagation: value written must become visible to others– Write serialization: writes to location seen in same order by all• if one processor sees w1 after w2, another processor should notsee w2 before w1• No need for analogous read serialization since reads not visible toothers.PCA page 276-277i.e processorsEECC756 - Shaaban#16 lec # 10 Spring2013 4-30-2013
Write Atomicity• Write Atomicity: Position in total order at which a writeappears to perform should be the same for all processes:Time– Nothing a process does after it has seen the new value producedby a write W should be visible to other processes until they toohave seen W.– In effect, extends write serialization to writes from multipleprocesses.P 1 P 2 P 3A=1;while (A==0);B=1;while (B==0);print A;•Problem if P 2 leaves loop, writes B, and P 3 sees new B but oldA (from its cache, i.e cache coherence problem).Old A?PCA page 289EECC756 - Shaaban#17 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15: Shared Memory Access Consistency•
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

EECC756 - Shaaban

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