EECC756 - Shaaban

More documents

Recommendations

Info

Non-Uniform Memory Access (NUMA)Example: AMD 8-way 8Opteron Server NodeCirca 2003Dedicated point-to-point interconnects (Coherent HyperTransport links) used toconnect processors alleviating the traditional limitations of FSB-based SMPsystems (yet still providing the cache coherency support needed)Each processor has two integrated DDR memory channel controllers:memory bandwidth scales up with number of processors.NUMA architecture since a processor can access its own memory at a lower latencythan access to remote memory directly connected to other processors in the system.Total 16 processor cores whendual core Opteron processors usedRepeated here from lecture 1EECC756 - Shaaban#8 lec # 10 Spring2013 4-30-2013
Chip Multiprocessor (Shared-Cache) Example:CMPIBM Power 4Two Processor cores on a chipshare level 2 cacheEECC756 - Shaaban#9 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7: Uniform Memory Access Example:Intel
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

EECC756 - Shaaban

Create successful ePaper yourself

Delete template?

Save as template?