EECC756 - Shaaban

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Invalidate Versus Update• Basic question of program behavior:– Is a block written by one processor read by others before it isrewritten (i.e. written-back)?• Invalidation:– Yes => Readers will take a miss.– No => Multiple writes without additional traffic.• Clears out copies that won’t be used again.• Update:– Yes => Readers will not miss if they had a copy previously.• Single bus transaction to update all copies.– No => Multiple useless updates, even to dead copies.• Need to look at program behavior and hardware complexity.• In general, invalidation protocols are much more popular.– Some systems provide both, or even hybrid protocols.EECC756 - Shaaban#34 lec # 10 Spring2013 4-30-2013
Update-Based Bus-Snooping Protocols• A write operation updates values in other caches.– New, update bus transaction.• Advantages:– Other processors don’t miss on next access: reduced latency• In invalidation protocols, they would miss and cause moretransactions.– Single bus transaction to update several caches can savebandwidth.• Also, only the word written is transferred, not whole block• Disadvantages:– Multiple writes by same processor cause multiple updatetransactions.• In invalidation, first write gets exclusive ownership, others local• Detailed tradeoffs more complex.Depending on program behavior/hardware complexityEECC756 - Shaaban#35 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33: MESI State Transition DiagramFour S
Page 37: Dragon State Transition DiagramS =

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