EECC756 - Shaaban

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Shared Memory MultiprocessorsCache DataInconsistency/CoherenceProblem• Direct support in hardware of shared address space (SAS)parallel programming model: address translation and protectionin hardware (hardware SAS).• Any processor can directly reference any memory location– Communication occurs implicitly as result of loads and stores• Normal uniprocessor mechanisms used to access data (loads andstores) + synchronization– Key is extension of memory hierarchy to support multipleprocessors. Extended memory hierarchy• Memory may be physically distributed among processors• Caches in the extended memory hierarchy may have multipleinconsistent copies of the same data leading to data inconsistencyor cache coherence problem that have to addressed by hardwarearchitecture.EECC756 - Shaaban#2 lec # 10 Spring2013 4-30-2013
Shared Memory Multiprocessors:Support of Programming ModelsMessage passingProgramming modelsShared address spaceCompilationor libraryMultiprogrammingCommunication abstractionUser/system boundaryOperating systems supportCommunication hardwarePhysical communication medium• Address translation and protection in hardware(hardware SAS).• Message passing using shared memory buffers:Hardware/software boundary• Can offer very high performance since no OS involvementnecessary.• The focus here is on supporting a consistent or coherentshared address space.EECC756 - Shaaban#3 lec # 10 Spring2013 4-30-2013
Page 1: Cache Coherence in Bus-Based Shared
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

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