EECC756 - Shaaban

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Basic Idea:Bus-Snooping Cache CoherenceProtocols• Transactions on bus are visible to all processors.• Processors or bus-watching (bus snoop) mechanisms can snoop(monitor) the bus and take action on relevant events (e.g. changestate) to ensure data consistency among private caches and sharedmemory.Basic Protocol Types:1• Write-invalidate:Invalidate all remote copies of when a local cache block isupdated.• Write-update:2When a local cache block is updated, the new data block is broadcast toall caches containing a copy of the block updating them.EECC756 - Shaaban#20 lec # 10 Spring2013 4-30-2013
Write-invalidate invalidate & Write-update CoherenceProtocols for Write-through through Caches• See handout• Figure 7.14 in Advanced ComputerArchitecture: Parallelism, Scalability,Programmability, Kai Hwang.EECC756 - Shaaban#21 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19: Cache Coherence Using A Bus• Buil
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35 and 36: Update-Based Bus-Snooping Protocols
Page 37: Dragon State Transition DiagramS =

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