EECC756 - Shaaban

More documents

Recommendations

Info

Dragon Write-back Update Protocol• 4 states:– Exclusive-clean or exclusive (E): I and memory have this block.– Shared clean (Sc): I, others, and maybe memory, but I’m not owner.– Shared modified (Sm): I and others but not memory, and I’m theowner.• Sm and Sc can coexist in different caches, with only one Sm.– Modified or dirty (D): I have this block and no one else, stale memory.• No explicit invalid state (implied).– If in cache, cannot be invalid.– If not present in cache, can view as being in not-present or invalid state.• New processor events: PrRdMiss, PrWrMiss.– Introduced to specify actions when block not present in cache.• New bus transaction: BusUpd.– Broadcasts single word written on bus; updates other relevant caches.PCA page 301Fifth (Invalid) State ImpliedThat was modified in owner’s cacheAlso requires “shared” signal Son bus (similar to MESI)EECC756 - Shaaban#36 lec # 10 Spring2013 4-30-2013
Dragon State Transition DiagramS = SharedS = Not SharedPrRd/—S = shared signal= 0 not shared= 1 sharedPrRd/—BusUpd/UpdateIPrRdMiss/BusRd(S)EBusRd/—ScIPrRdMiss/BusRd(S)Four States:E = ExclusiveSc = Shared cleanSm = Shared modifiedM = ModifiedSharedPrWrMiss/(BusRd(S); BusUpd)Not sharedBusUpd/UpdateUpdateothersSmPrWr/—SupplydataBusRd/FlushPrWr/BusUpd(S)SharedPrWr/BusUpd(S)Update othersMSharedPrWr/BusUpd(S)Not sharedPrWrMiss/BusRd(S)This Processoris ownerPrRd/—PrWr/BusUpd(S)BusRd/FlushSupply dataSharedBusUpd = Broadcast word written on bus to update other cachesNot sharedPrRd/—PrWr/—EECC756 - Shaaban#37 lec # 10 Spring2013 4-30-2013
Page 1 and 2: Cache Coherence in Bus-Based Shared
Page 3 and 4: Shared Memory Multiprocessors:Suppo
Page 5 and 6: Shared Memory Multiprocessors Varia
Page 7 and 8: Uniform Memory Access Example:Intel
Page 9 and 10: Chip Multiprocessor (Shared-Cache)
Page 11 and 12: Cache Coherence in Shared MemoryMul
Page 13 and 14: A Coherent Memory System: Intuition
Page 15 and 16: Shared Memory Access Consistency•
Page 17 and 18: Write Atomicity• Write Atomicity:
Page 19 and 20: Cache Coherence Using A Bus• Buil
Page 21 and 22: Write-invalidate invalidate & Write
Page 23 and 24: Coherence with Write-through throug
Page 25 and 26: Write-invalidate invalidate Bus-Sno
Page 27 and 28: Problems With Write-Through• High
Page 29 and 30: Write-invalidate Bus-Snooping Proto
Page 31 and 32: ThreeStates:Basic MSI Write-Back In
Page 33 and 34: MESI State Transition DiagramFour S
Page 35: Update-Based Bus-Snooping Protocols

EECC756 - Shaaban

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?