Power Optimization and Prediction Techniques for FPGAs - Jason H ...

List of Figures6.4 Finding the set of path lengths for y. . . . . . . . . . . . . . . . . . . . . . . . . . 1326.5 Zero-delay activity and predicted activity versus routed-delay activity. . . . . . . 1366.6 Logic-delay activity and predicted activity versus routed-delay activity. . . . . . 1376.7 Noise in interconnect capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . 1426.8 Illustration of parameter NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446.9 Routing congestion estimation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466.10 Average error for a variety of prediction models. . . . . . . . . . . . . . . . . . . 1486.11 Estimated versus actual values (approx. 4000 points in ellipse). . . . . . . . . . . 150xiii