Power Optimization and Prediction Techniques for FPGAs - Jason H ...

2.4 Power Dissipation in FPGAsLogic16%Interconnect60%IOBs10%Clocking14%Figure 2.12: Dynamic power breakdown in Xilinx Virtex-II [Shan 02].ration SRAM cells, and to a lesser extent, LUTs. Combined, these structures account for 88%of total leakage.As pointed out in [Tuan 03], the contents of an FPGA’s configuration SRAM cells changeonly during the FPGA’s configuration phase. Configuration is normally done once – at powerup.Therefore, the speed performance of an FPGA’s SRAM configuration cells is not critical, asit does not affect the operating speed of the circuit implemented in the FPGA. The SRAM cellscan be slowed down and their leakage can be reduced or eliminated using previously-publishedlow leakage memory techniques, such as those in [Kim 03], or by implementing the memorycells with high-V T H or long channel transistors. Leakage was not a primary consideration inthe design of Spartan-3. If SRAM configuration leakage were reduced to zero, the Spartan-3interconnect and LUTs would account for 55% and 26% of total leakage, respectively.Note that unlike ASICs, a design implemented in an FPGA uses only a portion of theunderlying FPGA hardware. Leakage is dissipated in both the used and the unused parts ofthe FPGA. To be sure, [Tuan 03] suggests that up to 45% of leakage in Spartan-3 is “unused”leakage (assuming reasonable device utilization). Notably, today’s commercial FPGAs do notyet offer support for a low leakage sleep mode for unused regions.27