Power Optimization and Prediction Techniques for FPGAs - Jason H ...

2.5 FPGA Power Optimization2.5.3 Dynamic Power Optimization (CAD Techniques)Figure 2.16 shows the typical FPGA CAD flow, comprised of HDL synthesis, technology mapping,clustering, placement, and routing. In the HDL synthesis step, an input design is synthesizedfrom a text description, typically VHDL or Verilog, into a circuit netlist, composed ofgeneric primitive elements from a target library. The library may consist of standard logic gates(for example, AND, OR, NOT) or it may contain FPGA-specific elements (for example, LUTs).In technology mapping, the synthesized circuit is transformed into elements that resemble thoseavailable in the target FPGA device, primarily LUTs and flip-flops. As mentioned above, logicblocks in commercial FPGAs contain multiple LUTs, flip-flops, as well as arithmetic and othercircuitry. A clustering or packing step is invoked after technology mapping to group LUTs andflip-flops into clusters corresponding to the logic blocks of the target FPGA. Placement assignsthe logic blocks in the design to logic block sites on the FPGA. Routing forms the desiredconnections between logic blocks. Finally, the routed design is translated into a configurationbitstream for programming the device.The potential for power optimization has been studied at each stage of the flow in Figure2.16. We briefly describe some of the published approaches below.Front-end SynthesisA power-aware HDL synthesis system for FPGAs was recently described in [Chen 03]. The systemleverages three observations that are unique to FPGAs: 1) datapath circuits often containlarge multiplexers, and implementing multiplexers in FPGAs imposes a substantial demand onLUTs and interconnect; 2) FPGAs contain a large number of registers – typically one registerper LUT; 3) interconnect accounts for the bulk of FPGA power consumption. The proposedsynthesis algorithm aims to reduce interconnect usage by trading-off the number of multiplexerports with register count. Through a 9% increase in register count, the number of multiplexerports is reduced by 23%, significantly reducing demand on interconnect. Considerablepower reductions of more than 30% are reported, in comparison with a commercial synthesis33