Power Optimization and Prediction Techniques for FPGAs - Jason H ...

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1 Introductionpower is mandatory if FPGAs are to break into the low-power ASIC market. Historically,applications such as portable or battery-powered electronics have been inaccessible to FPGAvendors, chiefly due to the tight power budgets they impose. For example, mobile applicationshave standby current limits of 10s to 100s of µA [Clar 02]. As few as 20 logic blocks in the XilinxSpartan-3 FPGA would exceed this standby current limit [Tuan 03]. In addition to broadeningthe FPGA market, lowering power consumption would reduce packaging and cooling costs,which represent a sizable fraction of the cost of an IC. Packaging costs for a 90nm design arepotentially on par with the cost of the silicon itself [Hawk 03]. Finally, it is worth noting thatcooler chips have better reliability, leading to long lifespans.In conjunction with reducing FPGA power, as power becomes a first-class design considerationfor FPGAs, efficient power-aware design will require new estimation tools that gauge powerdissipation at the early stages of the design process. Such tools would allow design trade-offsto be considered at a high level of abstraction, reducing design effort and cost.1.3 Thesis ContributionsThis dissertation focuses on two overarching themes:1. Reducing FPGA power consumption, including dynamic and static power.2. Early prediction of dynamic power consumption in FPGAs.With respect to these themes, a number of different contributions are made, as summarizedbelow.Chapter 3 considers active leakage power dissipation in FPGAs and presents two “no cost” approachesfor active leakage reduction 1 . It is well-known that the leakage power consumedby a digital CMOS circuit depends strongly on the state of its inputs. The first leakagereduction technique leverages a fundamental property of basic FPGA logic elements1 Active leakage is leakage in the used and operating part of an FPGA.4
1.3 Thesis Contributions(look-up-tables) that allows a logic signal in an FPGA design to be interchanged with itscomplemented form without any area or delay penalty. This property is applied to selectpolarities for logic signals so that FPGA hardware structures spend the majority of timein low leakage states. The second approach to leakage optimization consists of alteringthe routing step of the FPGA CAD flow to encourage more frequent use of routing resourcesthat have low leakage power consumptions. Such “leakage-aware routing” allowsactive leakage to be further reduced, without compromising design performance. In anexperimental study, active leakage power is optimized in circuits mapped into a stateof-the-art90nm commercial FPGA. Combined, the two approaches offer a total activeleakage power reduction of 30%, on average. This work has been published in [Ande 04f]and [Ande 05a]. To the author’s knowledge, this represents the first published work onactive leakage optimization in FPGAs.Chapter 4 presents circuit-level techniques for reducing power dissipation in FPGA interconnect.It proposes a family of new FPGA routing switch designs that are programmableto operate in three different modes: high-speed, low-power, or sleep. High-speed modeprovides similar power and performance to traditional FPGA routing switches. In lowpowermode, speed is curtailed in order to reduce power consumption. Leakage is reducedby 28-52% in low-power versus high-speed mode, depending on the particular switch designselected. Dynamic power is reduced by 28-31% in low-power mode. Leakage powerin sleep mode, which is suitable for unused routing switches, is 61-79% lower than inhigh-speed mode. Each of the proposed switch designs has a different power/area/speedtrade-off. All of the designs require only minor changes to a traditional routing switch,making them easy to incorporate into current FPGA interconnect. The applicability ofthe new switches is motivated through an analysis of timing slack in industrial FPGA designs.Specifically, it is observed that a considerable fraction of routing switches may beslowed down (operate in low-power mode), without impacting overall design performance.This work has been published in [Ande 04c], [Ande 04d], and [Ande 05b].5
Page 5 and 6: AcknowledgmentsThroughout my life,
Page 7 and 8: ContentsAcknowledgmentsList of Figu
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Page 13 and 14: List of Figures6.4 Finding the set
Page 15 and 16: List of Tables2.1 Summary of commer
Page 17 and 18: 1 Introduction1.1 Field-Programmabl
Page 19: 1.2 MotivationDespite the relative
Page 23 and 24: 1.4 Thesis Organizationto generic p
Page 25 and 26: 2 Background and Related Work2.1 In
Page 27 and 28: 2.2 Power Dissipation in CMOS Circu
Page 37 and 38: 2.3 FPGA Architecture and Hardware
Page 43 and 44: 2.4 Power Dissipation in FPGAsLogic
Page 45 and 46: 2.5 FPGA Power Optimizationeffect
Page 47 and 48: 2.5 FPGA Power Optimizationspeciali
Page 49 and 50: 2.5 FPGA Power Optimization2.5.3 Dy
Page 51 and 52: 2.5 FPGA Power OptimizationLUTswitc
Page 53 and 54: 2.5 FPGA Power OptimizationA B Z0 0
Page 55 and 56: 3 CAD Techniques for Leakage Optimi
Page 57 and 58: 3.2 FPGA Hardware Structuresdepende
Page 59 and 60: 3.2 FPGA Hardware StructuresV DDV D
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3.3 Active Leakage Power Optimizati
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3.5 Summaryrouting may increase dyn
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4 Circuit Techniques for Low-Power
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4.2 PreliminariesFigure 4.1: Sleep
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4.3 Low-Power Routing Switch Design
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4.4 Slack Analysis4.4 Slack Analysi
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4.5 Experimental StudyAverage % of
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4.5 Experimental Studymode in a typ
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4.5 Experimental Studyoutput logic-
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4.5 Experimental StudyTable 4.1: 85
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4.5 Experimental StudyTable 4.3: 85
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4.5 Experimental StudyTable 4.6: Dy
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4.5 Experimental Study1.8Normalized
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4.6 SummaryFPGAs. In this chapter,
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5 Power-Aware Technology Mapping5.1
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5.2 Preliminariesfrom x to z. The s
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5.2 PreliminariesLUTprimaryinputayb
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5.3 Algorithm DescriptionNodes(C a1
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5.3 Algorithm Descriptionof cut C z
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5.3 Algorithm DescriptionhizNodes(C
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5.4 Experimental Study and Resultsp
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5.4 Experimental Study and Resultsv
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5.4 Experimental Study and ResultsT
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5.4 Experimental Study and Resultsp
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5.6 Summaryhas been shown to signif
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6 Power Prediction Techniques6.1 In
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6.2 Backgroundcapacitance predictio
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6.3 Switching Activity PredictionTa
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6.3 Switching Activity Predictionpr
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6.3 Switching Activity Predictionin
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6.3 Switching Activity Predictionan
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6.3 Switching Activity Prediction12
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6.4 Interconnect Capacitance Predic
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6.5 Summaryalternate test circuit s
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7 Conclusions7.1 Summary and Contri
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7.2 Future Workactivity. Empirical
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7.2 Future WorkWith regard to early
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A Power Estimation Model Regression
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A.2 Capacitance PredictionTable A.2
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References[Abdo 02]A. Abdollahi, F.
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References[Betz 97b]V. Betz and J.
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References[Doyl 02][Farr 94]B. Doyl
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ReferencesLogic Timing Simulation
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References[Li 04a] F. Li and L.He.
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References[Poon 02a] K. Poon. “Po
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References[Stra 04] Stratix-II FPGA
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References[Zeit 04][Zuch 02]P. Zeit
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