Power Optimization and Prediction Techniques for FPGAs - Jason H ...

2.3 FPGA Architecture and Hardware Structuresi1i2i1i2s1s2SRAM celli1s1s1s1s1s1 s2s2s2s2s1s2i3s3s4i2i3s1s1s2s3i4i4s4a) decoded multiplexer b) encoded multiplexerc) multiplexer in 2-LUTFigure 2.11: Multiplexers as deployed in FPGA routing switches and a LUT.Given the discussion so far, the reader will appreciate that the multiplexer is perhaps themost important circuit element in an FPGA, since they are used extensively throughout theinterconnect and are also used to build LUTs. It is therefore worthwhile to review this structurein some detail. The multiplexers in FPGAs are typically implemented using NMOS transistortrees [Lemi 02]. Figures 2.11(a) and (b) depict multiplexers, as they would be deployed in arouting switch. Full CMOS transmission gates are generally not used to implement multiplexersin FPGAs because of their larger area and capacitance [Lemi 03]. Figures 2.11(a) and (b)show two possible implementations of a 4-to-1 multiplexer. Figure 2.11(a) shows a “decoded”multiplexer, which requires four configuration SRAM cells if used in an FPGA routing switch.Input-to-output paths through this decoded multiplexer consist of a single NMOS transistor.Figure 2.11(b) shows an “encoded” multiplexer that requires only two configuration SRAMcells, though has larger delay as its input-to-output paths consist of two transistors in series. Inlarger multiplexers, a combination of the designs shown in Figure 2.11 is also possible, allowingone to trade-off area for delay or vice-versa. In a LUT, the LUT inputs drive multiplexerselect signals; SRAM cells containing the truth table of the LUT’s logic function attach to the25