Power Optimization and Prediction Techniques for FPGAs - Jason H ...

2 Background and Related Work2.1 IntroductionThis chapter presents the background material that forms the basis for the research presented inlater chapters. Section 2.2 reviews power dissipation in CMOS circuits, covering both dynamic,as well as static power. Section 2.3 gives an overview of FPGA architecture and hardwarestructures, highlighting the features of two state-of-the-art commercial FPGAs. Section 2.4examines power dissipation in the FPGA context and discusses the breakdown of dynamic andstatic power dissipation in FPGAs. Section 2.5 surveys the recent literature on FPGA poweroptimization.2.2 Power Dissipation in CMOS CircuitsPower consumption in CMOS circuits can be classified as either dynamic or static. Dynamicpower consumption is due to the logic transitions that occur on the signals of a logic circuit.Such transitions occur as a normal part of useful computation, and dynamic power scales inproportion to the rate of computation. Static power, on the other hand, also referred to asleakage power, is dissipated when a logic circuit is in a quiescent state.2.2.1 Dynamic PowerDynamic power is consumed through two mechanisms: short-circuit current and the chargingand discharging of capacitance [Yeap 98]. Short-circuit current arises in a CMOS gate as itsoutput transitions between logic states. During a transition, both the pull-up and pull-down9