Power Optimization and Prediction Techniques for FPGAs - Jason H ...

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2 Background and Related Work100010.0Gate length (nm)1001.0Supply voltage (V)10750 350 180 95 45Process generation (nm)0.1Figure 2.4: Scaling of gate length and supply voltage [Doyl 02].nitude of V DD −V T H [Sedr 97]. Consequently, as supply voltages are reduced, threshold voltagesmust also be reduced to mitigate performance degradations. As discussed in Section 2.2.2, reducingV T H yields an exponential increase in subthreshold leakage. Thus, smaller feature sizesnecessitate lower supply voltages, which in turn necessitate lower threshold voltages, which areassociated with increased subthreshold leakage current. To be sure, subthreshold leakage ispredicted to increase by roughly 5X per process generation [Bork 99].Additionally, a transistor’s drive current depends linearly on its gate oxide capacitance, C ox ,defined as:C ox =εt ox(2.11)where ε is the permittivity of the gate insulator and t ox is the oxide thickness. Current drive isimproved by thinning the oxide (reducing t ox ), producing an exponential increase in gate oxideleakage 3 . Figure 2.5 (from [Taur 02]) illustrates the scaling of supply voltage, oxide thickness,and threshold voltage with process generation.The scaling trends outlined above imply that leakage power will constitute an increasinglydominant component of total power in future process technologies.A survey conducted by3 Thinner oxides are also required to maintain adequate gate control over the drain current as technologyscales [Fran 02].16
2.2 Power Dissipation in CMOS Circuits105Power supply and threshold voltage (V)210.50.20.1V DD1V THt ox5020105Gate oxide thickness (nm)20.02 0.05 0.1 0.2 0.5 1MOSFET channel length (microns)Figure 2.5: Scaling of V DD , V T H , and t ox with process generation [Taur 02].17
Page 5 and 6: AcknowledgmentsThroughout my life,
Page 7 and 8: ContentsAcknowledgmentsList of Figu
Page 10 and 11: Contentsx
Page 13 and 14: List of Figures6.4 Finding the set
Page 15 and 16: List of Tables2.1 Summary of commer
Page 17 and 18: 1 Introduction1.1 Field-Programmabl
Page 19 and 20: 1.2 MotivationDespite the relative
Page 21 and 22: 1.3 Thesis Contributions(look-up-ta
Page 23 and 24: 1.4 Thesis Organizationto generic p
Page 25 and 26: 2 Background and Related Work2.1 In
Page 27 and 28: 2.2 Power Dissipation in CMOS Circu
Page 31: 2.2 Power Dissipation in CMOS Circu
Page 37 and 38: 2.3 FPGA Architecture and Hardware
Page 43 and 44: 2.4 Power Dissipation in FPGAsLogic
Page 45 and 46: 2.5 FPGA Power Optimizationeffect
Page 47 and 48: 2.5 FPGA Power Optimizationspeciali
Page 49 and 50: 2.5 FPGA Power Optimization2.5.3 Dy
Page 51 and 52: 2.5 FPGA Power OptimizationLUTswitc
Page 53 and 54: 2.5 FPGA Power OptimizationA B Z0 0
Page 55 and 56: 3 CAD Techniques for Leakage Optimi
Page 57 and 58: 3.2 FPGA Hardware Structuresdepende
Page 59 and 60: 3.2 FPGA Hardware StructuresV DDV D
Page 61 and 62: 3.3 Active Leakage Power Optimizati
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3.4 Active Leakage Power Optimizati
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3.5 Summaryrouting may increase dyn
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4 Circuit Techniques for Low-Power
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4.2 PreliminariesFigure 4.1: Sleep
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4.3 Low-Power Routing Switch Design
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4.4 Slack Analysis4.4 Slack Analysi
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4.5 Experimental StudyAverage % of
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4.5 Experimental Studymode in a typ
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4.5 Experimental Studyoutput logic-
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4.5 Experimental StudyTable 4.1: 85
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4.5 Experimental StudyTable 4.3: 85
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4.5 Experimental StudyTable 4.6: Dy
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4.5 Experimental Study1.8Normalized
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4.6 SummaryFPGAs. In this chapter,
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5 Power-Aware Technology Mapping5.1
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5.2 Preliminariesfrom x to z. The s
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5.2 PreliminariesLUTprimaryinputayb
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5.3 Algorithm DescriptionNodes(C a1
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5.3 Algorithm Descriptionof cut C z
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5.3 Algorithm DescriptionhizNodes(C
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5.4 Experimental Study and Resultsp
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5.4 Experimental Study and Resultsv
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5.4 Experimental Study and ResultsT
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5.4 Experimental Study and Resultsp
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5.6 Summaryhas been shown to signif
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6 Power Prediction Techniques6.1 In
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6.2 Backgroundcapacitance predictio
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6.3 Switching Activity PredictionTa
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6.3 Switching Activity Predictionpr
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6.3 Switching Activity Predictionin
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6.3 Switching Activity Predictionan
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6.3 Switching Activity Prediction12
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6.4 Interconnect Capacitance Predic
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6.5 Summaryalternate test circuit s
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7 Conclusions7.1 Summary and Contri
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7.2 Future Workactivity. Empirical
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7.2 Future WorkWith regard to early
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A Power Estimation Model Regression
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A.2 Capacitance PredictionTable A.2
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References[Abdo 02]A. Abdollahi, F.
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References[Betz 97b]V. Betz and J.
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References[Doyl 02][Farr 94]B. Doyl
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ReferencesLogic Timing Simulation
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References[Li 04a] F. Li and L.He.
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References[Poon 02a] K. Poon. “Po
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References[Stra 04] Stratix-II FPGA
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References[Zeit 04][Zuch 02]P. Zeit
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