ECEN 454 Digital Integrated Circuit Design Lab9

Constraint options Worst Violations and All Violations apply only to the constraint report. Donot use them for timing reports.j) In the Timing Report Options section of the window, keep Path Delay Type as the defaultMaximum setting.k) Select Report Points and retain the Entire Path setting. Rise or fall delay is displayed foreach point in the path. This includes the incremental delay from the driver.l) Type 3 in the Max Paths to Show field to list the three paths with the longest delay.m) Click OK.n) Click Apply in the Report window.o) The timing report appears. It lists the three most critical paths in the design.4. Trace the critical pathp) Click the line in the Report Output window that displays the first cell in the path.q) Click Show. This action selects and zooms in the register (and pin) in the Schematic View.You can click Show again to enhance the highlighting.r) Continue click Next. This action highlights the points in the path.s) When you finish following the critical path, click Cancel. Remember, you must trace the firstcritical path for step u) to z)t) Select “Analysis->Highlight->Clear” to remove the highlighting on the path in theSchematic View. Then keep the schematic window.5. Use the Schematic View for AnalysisIt is not always necessary to generate reports to obtain timing or load values. You can displaythese values by selecting a pin on the schematic and requesting its timing.u) Select pin COMPARE_IN in the Schematic View. Note that COMPARE_IN is a pin of themodule ALARM_SM_2.v) Click the right mouse button in the Schematic View and select Show Timing in the menu.The Pin Values window appears and displays timing information.w) Click Cancel in the Pin Values window.Determine the load on a net.x) Select the net connecting COMPARE_IN to the COMPARATOR block.y) Select “Analysis −> Show Net Load”.