ECEN 454 Digital Integrated Circuit Design Lab9

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Click up-level-button (up arrow button on the left) to return the top level.Select TOP design.Select “Edit −> Uniquify −> Hierarchy”.Save the Design and run check_design again, you can see multiple design instances errordisappear.p) Select design TOP.q) Select “File −> Save As”.r) If you are not in the db directory, change to it.s) Type TOP_before_compile.db in the File Name Field.t) Verify that Save All Designs in Hierarchy option is set to on.u)Click OK.4. Optimize the DesignAfter setting constraints & attributes on the alarm clock design and running check_design, thedesign is ready to be optimized with the compile command. Optimizing is the step in thesynthesis process that attempts to implement a combination of library cells that meets thefunctional, area and speed requirements of the design.Detail procedure:Open the Design Optimization windowa) Return to the top level and select design Top.b) Select “Tools −> Design Optimization”.Check and set optionsc) Note the default settings. Map Design (mapping) is set to on. Map Effort is set toMedium. This is the CPU effort used to map a design. For most optimizations, thedefaults are sufficient to meet defined constraints.d) Set Verify Design to on. This checks that the new synthesized design is functionallyequivalent to the original design. Use Verify Effort value Low. This is the CPU effortused to verify the design.e) Set Allow Boundary Optimization to on.Open the Background Task window
f) Set Execute In to Background.g) Click OK. The Background Task window displays.h) In the Results Directory field, type the path name of the directory in which to store theresults. This directory must not already exist. The default value is~tutorial/compile_run.i) Click Ok. A compile_run window appears and displays the optimization activities. Thewindow name is the path name to your compile directory. By default, it is~tutorial/compile_run.Evaluate and Interpret the DesignGenerate reports to determine whether the design goals are met. Using Design Analyzer you canselect and generate any number of attribute and analysis reports, which send output to a report windowor a file you designate.1. Open the report windowa) Display the Symbol View of TOP.b) Select “Analysis −> Report”.2. Generate Attribute ReportsTake generating bus report as an example. The bus report lists bused ports and nets in thedesign.c)Select Bussing in the open Report window.d) Click Apply.3. Generate Analysis ReportsTake generating timing report as an example. A timing report provides timing information fordefined endpoints and constrained pins. If no endpoints or constrained pins are explicitly specified, thereport includes only timing information for the most critical path in the design.Select the timing report option.e) Click Clear Choices.f) Set Timing to on. When you set Timing to on, Set Options is enabled.g) Click Set Options in the Report window.h) In the Hierarchy Options section of the window, verify First Instance Only is set to on. Onlythe first occurrence of a submodule that is used multiple times in the hierarchy is shown.i) In the Constraint Options section of the window, set Verbose to on if it is not already set.
Page 3 and 4: Detail procedures:a) Analyze the bo
Page 5 and 6: Load values are used to model the c
Page 7: The design errors window appears.d)
Page 11 and 12: z) Click Cancel to close the Net Lo

ECEN 454 Digital Integrated Circuit Design Lab9

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