ECEN 454 Digital Integrated Circuit Design Lab9

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Enter TOP_attributes.db in the File Name field to save the file to db directory.Check the Save All Designs in Hierarchy option.Click Ok.m) Set the Optimization GoalsThe Optimization Goals include timing, area and power that you set on a design. DesignCompiler checks your optimization goals during optimization and tries to meet them whilesynthesizing the design to your technology library.Set Clock ConstraintsSelect CLK in the symbol view. Click“Attributes->Clocks->Specify”. Type 25in the Period field.Click Apply.Click Cancel to dismiss the Specify Clock window.The clock object is created on CLK. Note the small waveform symbol attached to the CLKport. Set Delay ConstraintsInput/Output delays model the external delays arriving/leaving at the input/output portsof the constrained module. In this Alarm clock design, the input delay is zero. We needto set the output delay.Select the four output ports of TOP.Select “Attributes->Operating Environment->Output Delay”.Select CLK.Enter 5 in the Max Rise and Max Fall fields.Click Apply.3. Run check_designClick Cancel to dismiss the Output delay window.a) Select “Analysis->Check Design”.b) Set Check Timing to on.c) Click Ok.
The design errors window appears.d) Click the first warning message in the design errors window.e) Click “Show”.Examine two more messages.f) Click Next in the Design Errors window to highlight the next message: Pin `T0' is connectedto logic 0. Pin T0 is selected in the schematic. Design Analyzer updates the schematic in theDesign Analyzer window.g) Click Next to highlight the next message. Pin T1 is selected in the schematic.h) Zoom in (from View menu on Design Analyzer window) on the area that contains pins T0and T1. The pin names for T0 and T1 are not displayed in the schematic because pin namesare turned off by default. Schematics are composed of transparent layers, each layercontaining different information. A layer of information is visible only if it is turned on.Display Pin Names Layeri) Select “View −> Style”.j) Select pin_name_layer. Set the Visible option to On.k) Click Apply. The schematic displays pin names.l) Click Cancel to dismiss the View Style window. Continue viewing errorsm) Click Next in the Design Errors window. This message is related to the earlier threemessages examined. Warning: In design `CONVERTOR_CKT', the same net is connected tomore than one pin on submodule `U7'. (LINT-33). This message and the previous threewarning messages are issued because unconnected input ports are automatically connected tologic 0 by Design Compiler. Because these warnings do not reflect problems in the design,you can ignore them. If you're using Verilog, the net name Logic 0 is connected to T0 andT1.n) Click Next in the Design Errors window. Warning: Design `CONVERTOR' is instantiated 2times. (LINT-45) Cell `U7' in design `CONVERTOR_CKT'. This message is issued becauseCONVERTOR is referenced more than once in design CONVERTOR_CKT. Resolve themultiple instances of CONVERTOR before optimization, as shown below in resolvingmultiple design instances.o) Click Cancel to dismiss the Design Errors window.Resolve Multiple Design InstancesHierarchical designs can reference a subdesign more than once. When the samesubdesign is referenced more than once in a design, multiple instances exist in thedesign. Resolve multiple design instances before you compile.
Page 3 and 4: Detail procedures:a) Analyze the bo
Page 5: Load values are used to model the c
Page 9 and 10: f) Set Execute In to Background.g)
Page 11 and 12: z) Click Cancel to close the Net Lo

ECEN 454 Digital Integrated Circuit Design Lab9

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