ECEN 454 Digital Integrated Circuit Design Lab9

f) Set Execute In to Background.g) Click OK. The Background Task window displays.h) In the Results Directory field, type the path name of the directory in which to store theresults. This directory must not already exist. The default value is~tutorial/compile_run.i) Click Ok. A compile_run window appears and displays the optimization activities. Thewindow name is the path name to your compile directory. By default, it is~tutorial/compile_run.Evaluate and Interpret the DesignGenerate reports to determine whether the design goals are met. Using Design Analyzer you canselect and generate any number of attribute and analysis reports, which send output to a report windowor a file you designate.1. Open the report windowa) Display the Symbol View of TOP.b) Select “Analysis −> Report”.2. Generate Attribute ReportsTake generating bus report as an example. The bus report lists bused ports and nets in thedesign.c)Select Bussing in the open Report window.d) Click Apply.3. Generate Analysis ReportsTake generating timing report as an example. A timing report provides timing information fordefined endpoints and constrained pins. If no endpoints or constrained pins are explicitly specified, thereport includes only timing information for the most critical path in the design.Select the timing report option.e) Click Clear Choices.f) Set Timing to on. When you set Timing to on, Set Options is enabled.g) Click Set Options in the Report window.h) In the Hierarchy Options section of the window, verify First Instance Only is set to on. Onlythe first occurrence of a submodule that is used multiple times in the hierarchy is shown.i) In the Constraint Options section of the window, set Verbose to on if it is not already set.