ECEN 454 Digital Integrated Circuit Design Lab9

Enter TOP_attributes.db in the File Name field to save the file to db directory.Check the Save All Designs in Hierarchy option.Click Ok.m) Set the Optimization GoalsThe Optimization Goals include timing, area and power that you set on a design. DesignCompiler checks your optimization goals during optimization and tries to meet them whilesynthesizing the design to your technology library.Set Clock ConstraintsSelect CLK in the symbol view. Click“Attributes->Clocks->Specify”. Type 25in the Period field.Click Apply.Click Cancel to dismiss the Specify Clock window.The clock object is created on CLK. Note the small waveform symbol attached to the CLKport. Set Delay ConstraintsInput/Output delays model the external delays arriving/leaving at the input/output portsof the constrained module. In this Alarm clock design, the input delay is zero. We needto set the output delay.Select the four output ports of TOP.Select “Attributes->Operating Environment->Output Delay”.Select CLK.Enter 5 in the Max Rise and Max Fall fields.Click Apply.3. Run check_designClick Cancel to dismiss the Output delay window.a) Select “Analysis->Check Design”.b) Set Check Timing to on.c) Click Ok.