ECEN 454 Digital Integrated Circuit Design Lab9

3. Also you need not set the Wire Load in this case.4. And for operating conditions use the "typical" option provided by the library.5. Use a clock period of 25 and set the output delay to 5 in both the Max Rise and Max Fall fields.Make sure you save the synthesized netlist (after performing optimization) of the design inverilog format. This file will be required for the next lab.Report Requirements:1. Print schematics of TOP and TIME_COUNTER.2. After performing the optimization of the Cruise Control Logic, print out the schematic of eachmodule in the circuit.3.Report the most critical path in the circuit,plot it out on the schematic window (MUST highlight it).4.Report the most critical path in the circuit, send the output to a file named "report.out",print the fileout.5.Print out the final synthesized verilog netlist of the cruise control logic.