ECEN 454 Digital Integrated Circuit Design Lab9

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Constraint options Worst Violations and All Violations apply only to the constraint report. Donot use them for timing reports.j) In the Timing Report Options section of the window, keep Path Delay Type as the defaultMaximum setting.k) Select Report Points and retain the Entire Path setting. Rise or fall delay is displayed foreach point in the path. This includes the incremental delay from the driver.l) Type 3 in the Max Paths to Show field to list the three paths with the longest delay.m) Click OK.n) Click Apply in the Report window.o) The timing report appears. It lists the three most critical paths in the design.4. Trace the critical pathp) Click the line in the Report Output window that displays the first cell in the path.q) Click Show. This action selects and zooms in the register (and pin) in the Schematic View.You can click Show again to enhance the highlighting.r) Continue click Next. This action highlights the points in the path.s) When you finish following the critical path, click Cancel. Remember, you must trace the firstcritical path for step u) to z)t) Select “Analysis->Highlight->Clear” to remove the highlighting on the path in theSchematic View. Then keep the schematic window.5. Use the Schematic View for AnalysisIt is not always necessary to generate reports to obtain timing or load values. You can displaythese values by selecting a pin on the schematic and requesting its timing.u) Select pin COMPARE_IN in the Schematic View. Note that COMPARE_IN is a pin of themodule ALARM_SM_2.v) Click the right mouse button in the Schematic View and select Show Timing in the menu.The Pin Values window appears and displays timing information.w) Click Cancel in the Pin Values window.Determine the load on a net.x) Select the net connecting COMPARE_IN to the COMPARATOR block.y) Select “Analysis −> Show Net Load”.
z) Click Cancel to close the Net Load window.6. Print the schematica) Select CONVERTOR_0 in the <strong>Design</strong>s View.b)Generate the Schematic View.c) Select “View −> Full View” to fit the schematic to the view window, then select “File −>Plot” in the menu bar.d) Select Current Sheet. Current Sheet prints only the sheet shown in the schematic view.e) In the Command: field, enter the print command for your local printer. Use the command “lp-d hpszac”.f) Click OK. Note that this file is not necessary in the lab report.7. Save the optimized verilog netlist.After completion of optimization save the design in the form a verilog netlist. Use “File-->SaveAs” and choose the Verilog option and save a copy of the “Top” design in the verilog folder as“Alarm_Clock.vh”.8.Synthesis of the Cruise Control LogicNow repeat the same procedure explained above to synthesize the behavioral verilog code thatwas written for the Cruise Control Logic of a vehicle in the previous lab session. But in this case weneed to synthesize the logic with a certain specific library for 180nm technology. The synopsysdatabase format(db) file for a typical 180nm technology is put up on the website. We need to ensurethat the synthesis is performed according to this library file(see below for procedure). What this meansis that the optimization (power, timing, area etc) will be performed according to the details of thestandard cells given in this file.Note: In the following lab we will use the synthesized verilog netlist that you will generate for thecruise control logic to “Place and Route” the circuit on a die.Procedure to link the given library with the synthesis process:1.Download the "iit018_stdcells.db" file from the lab website and save a copy in the ~/tutorial folder.2.After you begin <strong>Design</strong>_Analyzer , choose "Setup-->Defaults". A window pops up.3.Fill in iit018_stdcells.db in "Link Library".4.Fill in iit018_stdcells.db in "Target Library".5.Fill in generic.sdb in the "Symbol Library"6Click Ok.Now place the verilog behavioral code of the Cruise Control Logic in the ~/tutorial/verilog folder andrepeat the same procedure as above to optimize the logic and generate the synthesized netlist.Note:1. While assigning the drive strength for the clock, the above given procedure of usingdrive_of(class/B4I/Z) will not work since the target library does not remain the same. Hence use anabsolute value of 0.03352. Use a load of 3 on the output ports.
Page 3 and 4: Detail procedures:a) Analyze the bo
Page 5 and 6: Load values are used to model the c
Page 7 and 8: The design errors window appears.d)
Page 9: f) Set Execute In to Background.g)

ECEN 454 Digital Integrated Circuit Design Lab9

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