CS5531/32/33/34 - Eshop-Rychle.cz

CS5531/32/33/342.2.5. Reading/Writing On-Chip RegistersThe CS5531/32/33/34’s offset, gain, configuration,and channel-setup registers are readable and writablewhile the conversion data register is read only.As shown in Figure 7, to write to a particular registerthe user must transmit the appropriate writecommand and then follow that command by 32 bitsof data. For example, to write 0x80000000 (hexadecimal)to physical channel one’s gain register,the user would first transmit the command byte0x02 (hexadecimal) followed by the data0x80000000 (hexadecimal). Similarly, to read aparticular register the user must transmit the appropriateread command and then acquire the 32 bits ofdata. Once a register is written to or read from, theserial port returns to the command mode.In addition to accessing the internal registers one ata time, the gain and offset registers as well as thechannel setup registers can be accessed as arrays(i.e. the entire register set can be accessed with onecommand). In the CS5531/32, there are two gainand offset registers, and in the CS5533/34, there arefour gain and offset registers. There are four channelsetup registers in all parts. As an example, towrite 0x80000000 (hexadecimal) to all four gainregisters in the CS5533, the user would transmit thecommand 0x42 (hexadecimal) followed by four iterationsof 0x80000000 (hexadecimal), (i.e. 0x42followed by 0x80000000, 0x80000000,0x80000000, 0x80000000). The registers are writtento or read from in sequential order (i.e, 1, followedby 2, 3, and 4). Once the registers are writtento or read from, the serial port returns to the commandmode.2.3. Configuration RegisterTo ease the architectural design and simplify theserial interface, the configuration register is thirtytwobits long, however, only eleven of the thirtytwo bits are used. The following sections detail thebits in the configuration register.2.3.1. Power ConsumptionThe CS5531/32/33/34 accommodate three powerconsumption modes: normal, standby, and sleep.The default mode, “normal mode”, is entered afterpower is applied. In this mode, theCS5531/32/33/34-AS versions typically consume35 mW. The CS5532/34-BS versions typicallyconsume 70 mW. The other two modes are referredto as the power save modes. They power downmost of the analog portion of the chip and stop filterconvolutions. The power save modes are enteredwhenever the power down (PDW) bit of the configurationregister is set to logic 1. The particular powersave mode entered depends on state of the PSS(Power Save Select) bit. If PSS is logic 0, the converterenters the standby mode reducing the powerconsumption to 4 mW. The standby mode leavesthe oscillator and the on-chip bias generator for theanalog portion of the chip active. This allows theconverter to quickly return to the normal modeonce PDW is set back to a logic 1. If PSS and PDWare both set to logic 1, the sleep mode is entered reducingthe consumed power to around 500 µW.Since this sleep mode disables the oscillator, approximatelya 20 ms oscillator start-up delay periodis required before returning to the normal mode. Ifan external clock is used, there will be no delay.Further note that when the chips are used in theGain = 1 mode, the PGIA is powered down. Withthe PGIA powered down, the power consumed inthe normal power mode is reduced by approximately1/2. Power consumption in the sleep and standbymodes is not affected by the amplifier setting.2.3.2. System Reset SequenceThe reset system (RS) bit permits the user to performa system reset. A system reset can be initiatedat any time by writing a logic 1 to the RS bit in theconfiguration register. After the RS bit has beenset, the internal logic of the chip will be initializedto a reset state. The reset valid (RV) bit is set indicatingthat the internal logic was properly reset.DS289PP5 25