CS5531/32/33/34 - Eshop-Rychle.cz

CS5531/32/33/34φ1 Fineφ1 FineVREFφ2CoarseVREFφ2CoarseVos≤ 15 mVi n = fVosCC = 22pFMCLKf=16VRS = 1; 1 V ≤ V REF≤ 2.5 VV os≤ 30 mVi n = fVosCC = 11pFf=MCLK16VRS = 0; 2.5 V < V REF≤ VA+Figure 9. Input Reference Model when VRS = 1to limit drive currents to less than 20 µA to reduceself-heating of the chip. These outputs are poweredfrom VA+ and VA-. Their output voltage will belimited to the VA+ voltage for a logic 1 and VAfora logic 0.2.3.7. Offset and Gain SelectFigure 10. Input Reference Model when VRS = 0The Offset and Gain Select bit (OGS) is used to selectthe source of the calibration registers to usewhen performing conversions and calibrations.When the OGS bit is set to ‘0’, the offset and gainregisters corresponding to the desired physicalchannel (CS1-CS0 in the selected Setup) will be accessed.When the OGS bit is set to ‘1’, the offsetand gain registers pointed to by the OG1-OG0 bitsin the selected Setup will be accessed. This featureallows multiple calibration values (e.g. for differentgain settings) to be used on a single physical channelwithout having to re-calibrate or manipulate thecalibration registers.2.3.8. Filter Rate SelectThe Filter Rate Select bit (FRS) modifies the outputword rates of the converter to allow either 50 Hz or60 Hz rejection when operating from a 4.9152MHz crystal. If FRS is cleared to logic 0, the wordrates and corresponding filter characteristics can beselected (using the Channel Setup Registers) from7.5, 15, 30, 60, 120, 240, 480, 960, 1920, or 3840Sps when using a 4.9152 MHz clock. If FRS is setto logic 1, the word rates and corresponding filtercharacteristics scale by a factor of 5/6, making theselectable word rates 6.25, 12.5, 25, 50, 100, 200,400, 800, 1600, and 3200 Sps when using a 4.9152MHz clock. When using other clock frequencies,these selectable word rates will scale linearly withthe clock frequency that is used.DS289PP5 27