CS5531/32/33/34 - Eshop-Rychle.cz

CS5531/32/33/342.5.4. Performing CalibrationsTo perform a calibration, the user must send a commandbyte with its MSB=1, its pointer bits(CSRP2-CSRP0) set to address the desired Setup tocalibrate, and the appropriate calibration bits (CC2-CC0) set to choose the type of calibration to be performed.Note that calibration assumes that theCSRs have been previously initialized because theinformation concerning the physical channel, itsfilter rate, gain range, and polarity, comes from thechannel-setup register addressed by the pointer bitsin the command byte. Once the CSRs are initialized,a calibration can be performed with one commandbyte.The length of time it takes to do a calibration isslightly less than the amount of time it takes to doa single conversion (see Table 1 for single conversiontiming). Offset calibration takes 608 clock cyclesless than a single conversion when FRS = 0,and 729 clock cycles less when FRS = 1. Gain calibrationtakes 128 clock cycles less than a singleconversion when FRS = 0, and 153 clock cyclesless when FRS = 1.Once a calibration cycle is complete, SDO falls andthe results are automatically stored in either thegain or offset register for the physical channel beingcalibrated when the OGS bit in the ConfigurationRegister is set to ‘0’. If the OGS bit is set to ‘1’,the results will be stored in the register specified bythe OG1-OG0 bits of the selected Setup. See theOGS bit description for more details (Section2.3.7). SDO will remain low until the next commandword is begun. If additional calibrations areperformed while referencing the same calibrationregisters, the last calibration results will replace theeffects from the previous calibration as only oneoffset and gain register is available per physicalchannel. Only one calibration is performed witheach command byte. To calibrate all the channels,additional calibration commands are necessary.2.5.5. Self CalibrationThe CS5531/32/33/34 offer both self offset and selfgain calibrations. For the self-calibration of offset,the converters internally tie the inputs of the 1Xamplifier together and routes them to the AIN- pinas shown in Figure 11. For accurate self-calibrationof offset to occur, the AIN pins must be at the propercommon-mode-voltage as specified in the AnalogCharacteristics section. Self offset calibration usesthe 1X gain amplifier, and is therefore not valid inthe 2X-64X gain ranges. A self offset calibration ofthese gain ranges can be performed by setting the ISbitintheconfigurationregistertoa‘1’, and performinga system offset calibration. The IS bit must be returnedto ‘0’ afterwards for normal operation of thedevice.For self-calibration of gain, the differential inputsof the modulator are connected to VREF+ andVREF- as shown in Figure 12. Self-calibration ofgain will not work with (VREF+ - VREF-) > 2.5V.Self-calibration of gain is performed in the GAIN =1x mode without regard to the setup register’s gainsetting. Gain errors in the PGIA gain steps 2x to64x are not calibrated as this would require an accuratelow voltage source other than the referencevoltage. A system calibration of gain should be performedif accurate gains are to be achieved on theranges other than 1X, or when (VREF+ - VREF-) >2.5V.DS289PP5 33