CS5531/32/33/34 - Eshop-Rychle.cz

CS5531/32/33/34sult in the loss of synchronization between the microcontrollerand the ADC, and may prematurelyhalt the calibration cycle.For maximum accuracy, calibrations should be performedfor both offset and gain (selected by changingthe G2-G0 bits of the channel-setup registers).Note that only one gain range can be calibrated perphysical channel when the OGS bit in the ConfigurationRegister is set to ‘0’. Multiple gain rangescan be calibrated for a single channel by manipulatingthe OGS bit and the OG1-OG0 bits of the selectedSetup (see Section 2.3.7 for more details). Iffactory calibration of the user’s system is performedusing the system calibration capabilities ofthe CS5531/32/33/34, the offset and gain registercontents can be read by the system microcontrollerand recorded in non-volatile memory. These samecalibration words can then be uploaded into the offsetand gain registers of the converter when poweris first applied to the system, or when the gain rangeis changed.When the device is used without calibration, theuncalibrated gain accuracy is about ±1 percent andthe gain tracking from range (2X to 64X) to rangeis approximately ±0.3 percent.Note that the gain from the offset register to theoutput is 1.83007966 decimal, not 1. If a user wantsto adjust the calibration coefficients externally,they will need to divide the information to be writtento the offset register by the scale factor of1.83007966. (This discussion assumes that the gainregister is 1.000...000 decimal. The offset registeris also multiplied by the gain register before beingapplied to the output conversion words).2.5.8. Limitations in Calibration RangeSystem calibration can be limited by signal headroomin the analog signal path inside the chip asdiscussed under the Analog Input section of thisdata sheet. For gain calibration, the full scale inputsignal can be reduced to 3% of the nominal fullscalevalue. At this point, the gain register is approximatelyequal to 33.33 (decimal). While thegain register can hold numbers all the way up to 64-2 -24 , gain register settings above a decimal valueof 40 should not be used. With the converter’s intrinsicgain error, this minimum full scale input signalmay be higher or lower. In defining theminimum Full Scale Calibration Range (FSCR)under Analog Characteristics, margin is retained toaccommodate the intrinsic gain error. Inversely, theinput full scale signal can be increased to a point inwhich the modulator reaches its 1’s density limit of86 percent, which under nominal conditions occurswhen the full scale input signal is 1.1 times thenominal full scale value. With the chip’s intrinsicgain error, this maximum full scale input signalmaybe higher or lower. In defining the maximumFSCR, margin is again incorporated to accommodatethe intrinsic gain error.2.6. Performing ConversionsThe CS5531/32/33/34 offers two distinctly differentconversion modes. The three sections that followdetail the differences and provide examplesillustrating how to use the conversion modes withthe channel-setup registers.2.6.1. Single Conversion ModeBased on the information provided in the channelsetupregisters (CSRs), after the user transmits theconversion command, a single, fully-settled conversionis performed. The command byte includesa pointer address to the Setup register to be usedduring the conversion. Once transmitted, the serialport enters data mode where it waits until the conversionis complete. When the conversion data isavailable, SDO falls to logic 0. Forty SCLKs arethen needed to read the conversion data word. Thefirst 8 SCLKs are used to clear the SDO flag. Duringthe first 8 SCLKs, SDI must be logic 0. The last32 SCLKs are needed to read the conversion result.Note that the user is forced to read the conversionin single conversion mode as SDO will remain lowDS289PP5 35