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CS5531/32/33/34 - Eshop-Rychle.cz

CS5531/32/33/34 - Eshop-Rychle.cz

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<strong>CS5531</strong>/<strong>32</strong>/<strong>33</strong>/<strong>34</strong>2.12. Getting StartedThis A/D converter has several features. From asoftware programmer’s prospective, what shouldbe done first? To begin, a 4.9152 MHz or 4.096MHz crystal takes approximately 20 ms to start. Toaccommodate for this, it is recommended that asoftware delay of approximately 20 ms start theprocessor’s ADC initialization code. Next, sincethe <strong>CS5531</strong>/<strong>32</strong>/<strong>33</strong>/<strong>34</strong> do not provide a power-onresetfunction, the user must first initialize the ADCto a known state. This is accomplished by resettingthe ADC’s serial port with the Serial Port Initializationsequence. This sequence resets the serial portto the command mode and is accomplished bytransmitting 15 SYNC1 command bytes (0xFFhexadecimal), followed by one SYNC0 command(0xFE hexadecimal). Once the serial port of theADC is in the command mode, the user must resetall the internal logic by performing a system resetsequence (see 2.3.2 System Reset Sequence). Thenext action is to initialize the voltage referencemode. The voltage reference select (VRS) bit in theconfiguration register must be set based upon themagnitude of the reference voltage between theVREF+ and the VREF- pins.After this, the channel-setup registers (CSRs) shouldbe initialized, as these registers determine how calibrationsand conversions will be performed. Oncethe CSRs are initialized, the user has three options incalibrating the ADC: 1) don’t calibrate and use thedefault settings; 2) perform self or system calibrations;or 3) upload previously saved calibration resultsto the offset and gain registers. At this point,the ADC is ready to perform conversions.2.13. PCB LayoutFor optimal performance, the <strong>CS5531</strong>/<strong>32</strong>/<strong>33</strong>/<strong>34</strong>should be placed entirely over an analog groundplane. All grounded pins on the ADC, including theDGND pin, should be connected to the analogground plane that runs beneath the chip. In a splitplanesystem, place the analog-digital plane splitimmediately adjacent to the digital portion of thechip.Note:See the CDB5531/<strong>32</strong>/<strong>33</strong>/<strong>34</strong> data sheet forsuggested layout details and ApplicationsNote 18 for more detailed layout guidelines.Before layout, please call for our FreeSchematic Review Service.DS289PP5 45

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