CS5531/32/33/34 - Eshop-Rychle.cz

CS5531/32/33/34(i.e. the serial port is in data mode) until SCLKtransitions 40 times. After reading the data, the serialport returns to the command mode, where itwaits for a new command to be issued. The singleconversion mode will take longer than conversionsperformed in the continuous conversion mode. Thenumber of clock cycles a single conversion takesfor each Output Word Rate (OWR) setting is listedin Table 1. The ± 8 (FRS = 0) or ± 10 (FRS = 1)clock ambiguity is due to internal synchronizationbetween the SCLK input and the oscillator.Note:In the single conversion mode, more than oneconversion is actually performed, but only thefinal, fully settled result is output to theconversion data register.(WR3-WR0)Clock CyclesFRS = 0 FRS = 10000 171448 ± 8 205738 ± 100001 335288 ± 8 402346 ± 100010 662968 ± 8 795562 ± 100011 1318328 ± 8 1581994 ± 100100 2629048 ± 8 3154858 ± 101000 7592 ± 8 9110 ± 101001 17848 ± 8 21418 ± 101010 28088 ± 8 33706 ± 101011 48568 ± 8 58282 ± 101100 89528 ± 8 107434 ± 10Table 1. Conversion Timing for Single Mode2.6.2. Continuous Conversion ModeBased on the information provided in the channelsetupregisters (CSRs), continuous conversions areperformed using the Setup register contents pointedto by the conversion command. The command byteincludes a pointer address to the Setup register tobe used during the conversion. Once transmitted,the serial port enters data mode where it waits untila conversion is complete. After the conversion isdone, SDO falls to logic 0. Forty SCLKs are thenneeded to read the conversion. The first 8 SCLKsare used to clear the SDO flag. The last 32 SCLKsare needed to read the conversion result. If‘00000000’ is provided to SDI during the first 8SCLKs when the SDO flag is cleared, the converterremains in this conversion mode and continues toconvert the selected channel using the same CSRSetup. In continuous conversion mode, not everyconversion word needs to be read. The user needsonly to read the conversion words required for theapplication as SDO rises and falls to indicate theavailability of new conversion data. Note that if aconversion is not read before the next conversiondata becomes available, it will be lost and replacedby the new conversion data. To exit this conversionmode, the user must provide ‘11111111’ to the SDIpin during the first 8 SCLKs after SDO falls. If theuser decides to exit, 32 SCLKs are required toclock out the last conversion before the converterreturns to command mode. The number of clockcycles a continuous conversion takes for each OutputWord Setting is listed in Table 2. The first conversionfrom the part in continuous conversionmode will be longer than the following conversionsdue to start-up overhead. The ± 8 (FRS = 0) or ± 10(FRS = 1) clock ambiguity is due to internal synchronizationbetween the SCLK input and the oscillator.Note:When changing channels, or after performingcalibrations and/or single conversions, theuser must ignore the first three (for OWRsless than 3200 Sps, MCLK = 4.9152 MHz) orfirst five (for OWR ≥ 3200 Sps) conversions incontinuous conversion mode, as residualfilter coefficients must be flushed from thefilter before accurate conversions areperformed.FRS (WR3-WR0)Clock Cycles(First Conversion)Clock Cycles(All OtherConversions)0 0000 89528 ± 8 409600 0001 171448 ± 8 819200 0010 335288 ± 8 1638400 0011 662968 ± 8 3276800 0100 1318328 ± 8 6553600 1000 2472 ± 8 12800 1001 12728 ± 8 256036 DS289PP5