Dependable Memory - Laboratoire Interface Capteurs ...

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8 GENERAL INTRODUCTION system boundaries to cause catastrophic failures 1 . Consequently, the hardware based concurrent error detection (CED) has been chosen. To limit the overall cost, we may accept little time penalty in error correction. In this scenario, the software based rollback is employed. It will reduce the overall cost as compared to hardware based recovery. Whereas, it will not effect lot to overall performance because the proposed methodology is suitable for ground applications where occurrence of error is far less than space. There is a hypothetical dependable memory (DM) attached to the processor. Moreover, to make the rollback fast and to simplify the memory management there is an intermediate data storage between processor and DM. Here, architectural choices are important to make the overall methodology successful. For-example, the processor core having minimum internal states to be checked (for detect- ing error) and load and store (for rollback recovery) can make this technique effective (less expensive and fast). The FT processor has been modeled at VHDL-RTL level. Finally, the processor self checking ability and performance degradation due to re-execution has been tested by artificial error injection in the simulated model. The contributions of this work are as follows: Proposing a new methodology based on hardware/software co-design to have a compromise between protection and time/area constrains. For fast error detection, hardware based concurrent detection is employed. For low hardware overheads, software based micro-rollback recovery will be used. To reduce the overall area overheads we are em- ploying stack processor from MISC class. The processor has minimum internal registers which result in low cost error detection and on the other hand it is suitable for efficient error recovery. Further- more to mask the error from entering into DM, the intermediate temporal data storage is introduced between processor and DM. This thesis is partitioned into six chapters. Chapter 1: It outline the background and describe the motivation for on-line error detection and fast correction in embedded microprocessors. It present the basic concepts and the terminologies related to dependable embedded processor design. It further explores attributes, threats and means to attain dependability. Lastly, the different dependability techniques applied at different levels are discussed. Chapter 2: This chapter will be presenting different redundancy techniques to detect and correct errors. It explores different FT methodologies employed in the existing fault tolerant processors. The last part will be dedicated to the validation methodology of a dependable processor. Chapter 3: This chapter identifies the model specifications and design methodology of the desired architecture. It address the overall problem by exploring the design paradigm and the related constrains of the proposed approach. Later the processor-memory interface will be finalized by different functional implementations. Chapter 4: The proposed FT processor has two parts: self-checking processor core (SCPC) and self-checking hardware journal (SCHJ). This chapter steps towards a design methodology of self- 1 where the cost of harmful consequences is orders of magnitude, or even incommensurably, higher than the benefit provided by correct service delivery [LRL04]
checking processor core (SCPC). The processor will be chosen from the MISC (minimum instruction set computer) class; therefore, firstly, we clarify the reasons of choosing such a specialized processor. Later on, error detection and recovery mechanism are finalized. Finally, the hardware model of the self-checking processor core will be synthesized on Altera, Quartus II Stratix III. Chapter 5: The chapter discusses the hardware design and protection scheme of a self-checking hardware journal (SCHJ), which will be temporary data storage to mask errors from entering into the dependable main memory. Finally, the overall hardware model of the FT processor will be synthesized on Altera, Quartus II Stratix III. Chapter 6: Lastly, the FT model will be evaluated in presence of errors. The evaluation will be based on the self-checking and performance degradation in presence of errors. Hence, the obtained results validate the protection techniques proposed in the chapter 3. Finally, the last section will be discussing conclusions and perspectives. 9
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 8 and 9: 2 CONTENTS 2.3 Error Recovery . . .
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13: General Introduction owadays, devic
Page 17: I. STATE OF ART 11
Page 20 and 21: 14 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
Page 59 and 60: Chapter 3 Design Methodology and Mo
Page 61 and 62: 3.2. METHODOLOGY 55 further investi
Page 63 and 64: 3.2. METHODOLOGY 57 software techni
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3.5. DESIGN CHALLENGES 59 3.5 Desig
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3.5. DESIGN CHALLENGES 61 Self-Chec
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3.6. MODEL SPECIFICATIONS AND GLOBA
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3.7. FUNCTIONAL IMPLEMENTATION 65 (
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3.7. FUNCTIONAL IMPLEMENTATION 67 n
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3.7. FUNCTIONAL IMPLEMENTATION 69 C
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3.7. FUNCTIONAL IMPLEMENTATION 71 C
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3.8. CONCLUSIONS 73 Free space Data
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3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
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Chapter 4 Design and Implementation
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4.1. PROCESSOR DESIGN STRATEGY 79 F
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4.2. PROPOSED ARCHITECTURE 81 2 Num
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4.3. HARDWARE MODEL OF THE STACK PR
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4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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