Dependable Memory - Laboratoire Interface Capteurs ...

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28 CHAPTER 1. DEPENDABILITY AND FAULT TOLERANCE Fault Avoidance Fault Masking Specification Mistakes Implementation External Disturbances Component Defects Specification Mistakes Implementation Hardware Faults Software Faults Fault Tolerance Errors Errors Figure 1.11: Dependability techniques. Error Detection Recovery System Failure System Failure our final objective is the design of a fault tolerant computing system against single event effect such as SEUs (Single Event Upsets). In addition, this chapter is addressing the dependability issues against non-permanent disturbances. Our goal is to propose a new design methodology of dependable processor architectures. Consequently, in chapter 2, we will discuss some existing methodologies of detecting and correcting errors.
1.7. CONCLUSIONS 29 Ionization Different Fault tolerance levels Transient Current Sensors (detectors) Time redundancy (detection migration) Fault Latency Transient Voltage Pulse Fault Effect Flip-Flop Error Failure Hardware Redundancy Error correction codes (detection & migration) Error Latency a b c d e Self checking mechanism with recovery (detection & migration) Fault Tolerant at level c & d in figure has been addressed in this thesis Figure 1.12: Sequence of events from ionization to failure and a set of fault tolerant techniques applied at different time. [Pie07]. Redundancy/ spare components
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 8 and 9: 2 CONTENTS 2.3 Error Recovery . . .
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13 and 14: General Introduction owadays, devic
Page 15 and 16: checking processor core (SCPC). The
Page 17: I. STATE OF ART 11
Page 20 and 21: 14 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
Page 59 and 60: Chapter 3 Design Methodology and Mo
Page 61 and 62: 3.2. METHODOLOGY 55 further investi
Page 63 and 64: 3.2. METHODOLOGY 57 software techni
Page 65 and 66: 3.5. DESIGN CHALLENGES 59 3.5 Desig
Page 67 and 68: 3.5. DESIGN CHALLENGES 61 Self-Chec
Page 69 and 70: 3.6. MODEL SPECIFICATIONS AND GLOBA
Page 71 and 72: 3.7. FUNCTIONAL IMPLEMENTATION 65 (
Page 73 and 74: 3.7. FUNCTIONAL IMPLEMENTATION 67 n
Page 75 and 76: 3.7. FUNCTIONAL IMPLEMENTATION 69 C
Page 77 and 78: 3.7. FUNCTIONAL IMPLEMENTATION 71 C
Page 79 and 80: 3.8. CONCLUSIONS 73 Free space Data
Page 81 and 82: 3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
Page 83 and 84: Chapter 4 Design and Implementation
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4.1. PROCESSOR DESIGN STRATEGY 79 F
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4.2. PROPOSED ARCHITECTURE 81 2 Num
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4.3. HARDWARE MODEL OF THE STACK PR
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4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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