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36 CHAPTER 2. METHODS TO DESIGN AND EVALUATE FT PROCESSORS When data is retrieved, a parity checker is used to compute the parity based on data bit stored. The parity checker compares the computed parity and the stored parity and an error signal is set accord- ingly. Similarly, parity coding can also be used to protect the logic functions (see the figure 2.7). It is used commonly in computers to check errors in busses, memory, and registers [IK03]. Input Input parity F P comparator Figure 2.7: Functional Parity Output Output parity Error Signal Cyclic redundancy checks (CRCs) is another class of EDC. It is commonly employed to detect errors in digital system [IK03]. Cyclic codes are parity check codes with the additional property that the cyclic shift of a codeword is also a codeword. If then (Cn−1, Cn−2, ...C1, C0) is a codeword, (Cn−2, Cn−3, ...C0, Cn−1) is also a codeword. The idea is to append a checksum to the end of the data frame in such a way that the polynomial represented by the resulting frame is divisible by the generator polynomial G(x) that the sender and receiver have agreed upon. When the receiver gets the checksummed frame, it divides it by G(x) and if the remainder is not zero, there has been a transmission error. It is then clear that the best generator polynomials are those less likely to divide evenly into a frame that contains errors. CRCs are distinguished by the generator polynomials they use. It cannot directly specify the error bit position during the decoding process. Hence it is only limited for error detection. The Borden codes are another class of codes that can detect unidirectional errors (errors that cause either a 0 → 1 or 1 → 0 transition, but not both). It is the optimal code for unidirectional error detection. The Berger EDC is capable of detecting all unidirectional errors. It is formulated by appending check bit to the data word. The check bit constitute the binary representation of the number of 0 ′ s in the data word. For example, in 3-bit long data word, we need 2-bit for the check. Berger code is simpler to deal than the Borden codes. The Bose code is more efficient than the Berger code. The Bose code provides the same error detecting capability that the Berger code does, but with fewer checks bit. Briefly, on increasing the complexity of the codes the efficiency of the codes increases. Choosing the right code depends on the application needs. In arithmetic processing circuits (such as in ALU) the previously discussed codes are incapable of detecting errors because when two data symbols are subjected to an arithmetic operations, it result in
2.1. ERROR DETECTION 37 a new data symbol which cannot be uniquely expressed as the combination of inputs [FP02, Nic02]. In other words, they are useful in checking arithmetic operations, where parity would not be preserved [FP02, IK03]. The information parts of an operand are processed through a typical arithmetic operator, while a check symbol is concurrently generated (based on the information bits) [Bic10]. They have two classical implementation: AN and residue codes. AN codes are the simplest form of arithmetic codes [Muk08]. They are formed by multiplying each data word ‘N’ by a constant ‘A’. The following equation gives an example of an AN code: A (N1 + N2) = A (N1) + A (N2) (2.1) They are preserved only under arithmetic operations and they are not valid for logical and shift operations. They are not commonly employ due to their high hardware and timing penalty. Figure 2.8: Residue codes adder [FFMR09]. Residue codes are another type of arithmetic code, in which the information to be used in checking is called the residue. The residue, r, of an operand, A, is equal to the remainder of ‘A’ divided by the modulo-base ‘m’ [Bic10]. Both the computations occur simultaneously (see figure 2.8). For the first computation step, two operands, A and B, undergo an arithmetic operation in the ALU. A residue generator then produces a residue code from the ALU result. For the computation, each operand concurrently enters a residue generator. These residues then undergo the same ALU operation as in the first computation (addition in this case) [FFMR09]. Finally the residue is compared to find the errors.
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 8 and 9: 2 CONTENTS 2.3 Error Recovery . . .
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13 and 14: General Introduction owadays, devic
Page 15 and 16: checking processor core (SCPC). The
Page 17: I. STATE OF ART 11
Page 20 and 21: 14 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
Page 59 and 60: Chapter 3 Design Methodology and Mo
Page 61 and 62: 3.2. METHODOLOGY 55 further investi
Page 63 and 64: 3.2. METHODOLOGY 57 software techni
Page 65 and 66: 3.5. DESIGN CHALLENGES 59 3.5 Desig
Page 67 and 68: 3.5. DESIGN CHALLENGES 61 Self-Chec
Page 69 and 70: 3.6. MODEL SPECIFICATIONS AND GLOBA
Page 71 and 72: 3.7. FUNCTIONAL IMPLEMENTATION 65 (
Page 73 and 74: 3.7. FUNCTIONAL IMPLEMENTATION 67 n
Page 75 and 76: 3.7. FUNCTIONAL IMPLEMENTATION 69 C
Page 77 and 78: 3.7. FUNCTIONAL IMPLEMENTATION 71 C
Page 79 and 80: 3.8. CONCLUSIONS 73 Free space Data
Page 81 and 82: 3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
Page 83 and 84: Chapter 4 Design and Implementation
Page 85 and 86: 4.1. PROCESSOR DESIGN STRATEGY 79 F
Page 87 and 88: 4.2. PROPOSED ARCHITECTURE 81 2 Num
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Page 91 and 92: 4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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