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2.4. FT PROCESSOR DESIGN TRENDS 43
branch address is calculated. The processor takes a minor performance hit but is able to continue
correct instruction execution.
Tags for level-1 instruction and data caches are parity-protected. Both level-1 caches are inclusion
caches; tag information is duplicated in the level-2 tag. When a parity error is detected in a level-1 tag
access, the level-2 tag is interrogated for the correct copy of the tag. The level-1 cache access is then
re-executed. The last major SRAM array on the chip is the Translation Look-aside Buffer (TLB).
TLB is protected by parity check and a parity error in the TLB is treated as a miss. The correct
page table entry is fetched from the ECC-protected main memory during re-execution. In addition
to implementing cache and TLB protection, the SPARC64 V is designed to detect single bit SRAM
errors in other smaller SRAM arrays and recover from those errors as well.
The processor logic circuits are protected by byte parity check to detect single bit logic errors in
each byte. Parity check bits are calculated at the location of new data value generation and passed
with the associated data through the processor logic circuits. Parity bits are checked at the receiving
end.
Arithmetic/logic units are equipped with byte parity predictors. The byte parity predictors calcu-
late the parity bits for each output byte of an arithmetic/logic unit using the same input signals as the
unit to be checked. These independently calculated byte parity bits are compared with the byte parity
bits calculated from the output of the arithmetic/logic unit. Multipliers are checked with a modulo-3
scheme.
The byte parity predictors in the arithmetic/logic unit do not detect point errors that result in an
even number of bit flips in the output byte, and the modulo-3 scheme used in the multipliers do
not detect point errors that give the same modulo-3 residue. These checks, however, do detect the
majority of single point errors and are cost-effective compared to a full duplication and compare
implementation. When a parity error is detected in the logic circuits or small SRAM arrays, the
processor stops issuing new instructions and clears all intermediate states. It then restarts execution
at the instruction directly following the last correctly executed instruction by using the check-pointed
states. This action is called instruction retry.
The checkpoint and instruction retry mechanisms are implemented in the processor for recovery
from branch misprediction. Thus, the additional cost associated with utilizing these mechanisms for
error recovery is small. Furthermore, many microprocessors today feature either ECC or byte parity
for large on-chip SRAM arrays. Compared with those microprocessors, the SPARC64 V micropro-
cessor only requires additional transistors for implementing byte parity bits, byte parity predictors and
the associated parity checkers in the logic circuits and small SRAM arrays. The number of transistors
devoted to the error detection mechanisms of the SPARC64-V microprocessor is about 10% of the
transistors for logic gates, latches and parity-protected small SRAM arrays.
LEON3 FT
LEON3 is the successor of the LEON2 processor developed for the European Space Agency