Dependable Memory - Laboratoire Interface Capteurs ...

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22 CHAPTER 1. DEPENDABILITY AND FAULT TOLERANCE Fault Error Failure fault z 0 1 always A=1 1 1 0 error Traffic Control system Figure 1.7: A single fault caused failure of traffic control system Correct Service 1.4.2 Characteristics of a Fault Service failure Service restoration Figure 1.8: service failure Incorrect Service Correct signal Wrong signal Faults can be characterized by five attributes, which are cause, nature, duration, extend and value. Figure 1.9 illustrates each of these basic characteristics of faults. They are discussed in the following section. Cause Possible fault can be caused due to four salient problems: 1. Specifications Mistakes: These include incorrect algorithms, architectures, or incorrect design
1.4. THREATS 23 Fault Characteristics Cause Nature Duration Extent Value Specification Mistakes Implementation External Disturbances Component Defects Software Hardware Transient Intermittent Permanent Local Global Determinate Indeterminate Figure 1.9: Fault characteristics. HDL Programming Logical Electronic CMOS Digital Analog specifications, as in row 1 of figure 1.10 where there is fault caused by the wrong interconnec- tion between the two systems. 2. Implementation Mistakes: The implementation can introduce faults due to poor design, poor component selection, poor construction, or hardware/software coding mistakes as in rows 2 and 3 of figure 1.10. The row 2 shows the programming fault in which c is incremented if a is less than b but c will not be incremented if a is equal to b which is a programming error. Similarly in row 3 of figure 1.10, r1 charge the result of addition a+b in the register c. 3. Components Defects: These include random device defects, manufacturing imperfections, and component wear-out. It can be a logical component or electronic CMOS. As shown in the row 4 and 5 of figure 1.10 4. External Disturbance: These include operator mistakes, radiation, electromagnetic interfer- ence, and environment extremes. As in row 6 of the figure. 1.10. Moreover, due to reducing noise margin the ‘1’ can be read as ‘0’ if its value is lower than threshold (Vm) (as shown in row 7 of the figure. 1.10).
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 8 and 9: 2 CONTENTS 2.3 Error Recovery . . .
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13 and 14: General Introduction owadays, devic
Page 15 and 16: checking processor core (SCPC). The
Page 17: I. STATE OF ART 11
Page 20 and 21: 14 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
Page 59 and 60: Chapter 3 Design Methodology and Mo
Page 61 and 62: 3.2. METHODOLOGY 55 further investi
Page 63 and 64: 3.2. METHODOLOGY 57 software techni
Page 65 and 66: 3.5. DESIGN CHALLENGES 59 3.5 Desig
Page 67 and 68: 3.5. DESIGN CHALLENGES 61 Self-Chec
Page 69 and 70: 3.6. MODEL SPECIFICATIONS AND GLOBA
Page 71 and 72: 3.7. FUNCTIONAL IMPLEMENTATION 65 (
Page 73 and 74: 3.7. FUNCTIONAL IMPLEMENTATION 67 n
Page 75 and 76: 3.7. FUNCTIONAL IMPLEMENTATION 69 C
Page 77 and 78: 3.7. FUNCTIONAL IMPLEMENTATION 71 C
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3.8. CONCLUSIONS 73 Free space Data
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3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
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Chapter 4 Design and Implementation
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4.1. PROCESSOR DESIGN STRATEGY 79 F
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4.2. PROPOSED ARCHITECTURE 81 2 Num
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4.3. HARDWARE MODEL OF THE STACK PR
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4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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