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40 CHAPTER 2. METHODS TO DESIGN AND EVALUATE FT PROCESSORS Among them, Reed Soloman codes are cyclic codes that require complex encoding and decoding circuitry and are especially well-suited to applications where errors occur in bursts. That’s why they are mostly employed in channel coding. On the other hand, convolution coding schemes are useful in data storage and transmission systems, such as memory and data networks [FP02]. 2.3 Error Recovery Recovery transforms a system state that contains one or more errors and (possibly) faults into another state without detected errors and faults that can be activated again [ALR01]. Error recovery can only be initiated on detection of fault/error, therefore, the system should have built-in self checking mechanism. Nowadays, modern microprocessors have variable built-in error detection capabilities like, error detection in memory, cache, registers, illegal op-code detection, and so on [MBS07]. It can be higher level based on error handling (eliminate error from the system states) or lower level based on fault handling (prevent fault from being activated again). Recovery hides the consequences of faults from the user. It is more adequate for transient and intermittent faults, whereas, for permanent fault, the recovery is generally not sufficient. It needs one mandatory feature that is fault handling (see figure 2.11), it eliminates faults from the system state [LB07]. The fault-handling feature prevents faults from being activated again. This requires further features such as diagnosis, which reveals and localizes the cause(s) of error(s) [LRL04]. Diagnosis can also enable a more effective error handling. If the cause of the error is localized, the recovery procedure can take actions concerning the associated components without affecting the other parts of the system and related system functionality. In this work, we will be addressing the soft errors caused due to transient faults. Therefore, fault handling technique will not be important to explore. There are two sub-types of error recovery; forward error recovery (FER) and backward error recovery (BER). In FER, the system does not need to restore its states but it continues to make forward progress without restoring the system states. The compensator will overcome the faults (as shown in figure 2.11 (FER)). For example, in TMR the voter will mask (compensate) the fault and in ECC the error correcting circuitry will correct the (corrigible) error. BER involves restoring the states of the system to a previous known sure states. In otherwords, the state transformation consists of returning the system back to a saved state that existed prior to error detection [ALR01]. For the successful BER the system must be aware of the following facts: (i) which and where states are to be saved for recovery point; (ii) which algorithm to use; and (iii) what the system do after recovery. There are two known algorithms for saving the BER recovery states: checking point and logging. The choice depends on the micro-architecture of the core and recovery requirements, because both have different costs for different types of states and many BER systems use hybrid of both. A system presented in [SMHW02] uses hybrid BER. An actual criterion of choice is that if we have few registers and recoveries are not frequent, then check pointing is preferred. If there are many registers and frequent recovery then logging will be preferred.
2.4. FT PROCESSOR DESIGN TRENDS 41 Backward Error Recovery (BER) Forward Error Recovery (FER) Maintenance Call Error Detection Rollback Permanent fault Fault Handling Transient - Intermittent faults No Yes Service Continuation Permanent fault Fault Handling No Maintenance Call Error Detection Compensation Yes Transient - Intermittent faults Service Continuation Figure 2.11: Basic strategies for implementing Error Recovery. Another important aspect is where to save the states of the recovery point. A shadow register file is created in the core to save the states of the sensitive elements. The backup values in the shadow copy can be used for rollback and recovery [AHHW08]. However, some other techniques, which require high reliability, store the states of internal registers off-chip. When the states are recovered the ECC are employed to avoid possible errors. In the recent era, a lot of development has been done in BER and many low cost computers employ BER. Like IBM is employing checkpoint recovery in POWER-6 micro-architecture [MSSM10]. 2.4 FT Processor Design Trends Recently, fault-tolerant computing has begun to draw more and more attention in a wider range of industrial and academic communities, due to increased safety and reliability demand [ZJ08]. Today, FT is the need of real time industrial application [RI08]. Mostly, high cost solutions are not acceptable for the industry, consequently the modern processors avoid hardware replication and tend to employ alternate techniques having lower power and area overheads (like information redundancy or hybrid redundancy). Information redundancy (like employing ECC) have less hardware overhead, however
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 8 and 9: 2 CONTENTS 2.3 Error Recovery . . .
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13 and 14: General Introduction owadays, devic
Page 15 and 16: checking processor core (SCPC). The
Page 17: I. STATE OF ART 11
Page 20 and 21: 14 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
Page 59 and 60: Chapter 3 Design Methodology and Mo
Page 61 and 62: 3.2. METHODOLOGY 55 further investi
Page 63 and 64: 3.2. METHODOLOGY 57 software techni
Page 65 and 66: 3.5. DESIGN CHALLENGES 59 3.5 Desig
Page 67 and 68: 3.5. DESIGN CHALLENGES 61 Self-Chec
Page 69 and 70: 3.6. MODEL SPECIFICATIONS AND GLOBA
Page 71 and 72: 3.7. FUNCTIONAL IMPLEMENTATION 65 (
Page 73 and 74: 3.7. FUNCTIONAL IMPLEMENTATION 67 n
Page 75 and 76: 3.7. FUNCTIONAL IMPLEMENTATION 69 C
Page 77 and 78: 3.7. FUNCTIONAL IMPLEMENTATION 71 C
Page 79 and 80: 3.8. CONCLUSIONS 73 Free space Data
Page 81 and 82: 3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
Page 83 and 84: Chapter 4 Design and Implementation
Page 85 and 86: 4.1. PROCESSOR DESIGN STRATEGY 79 F
Page 87 and 88: 4.2. PROPOSED ARCHITECTURE 81 2 Num
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Page 91 and 92: 4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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