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34 CHAPTER 2. METHODS TO DESIGN AND EVALUATE FT PROCESSORS Input F Output t t+δ t comparator buffer Error Signal Figure 2.3: Time redundancy for temporary and intermittent fault detection is first encoded in some manner. The results of the computation are then decoded and the results are compared to the results produced before. Any discrepancy will detect a permanent fault in the functional block. Input t t+δ t Encoder Encoder F t t+δ t buffer Decoder comparator Output Error Signal Figure 2.4: Time redundancy for permanent error detection An alternative approach can be redundant execution with shifted operands (RESO) [PF06] where some instructions are executed redundantly with shifted operands on the same functional units. Shift- ing the result back by the same amount yields the original result computed with un-shifted operands. Re-executing instructions detects transient faults whereas re-executing with shifted operands also detects permanent faults. Scheme works when functionality possesses required properties such as linearity Time redundancy directly affects the system performance although the hardware cost is generally less than that of hardware redundancy. Therefore temporal redundancy based systems are compara- tively slower. In order to overcome this issue, many systems use pipelining to hide the latency issue from the client. The temporal redundancy does not address energy consequence at all, except it uses twice as much active power as a non-redundant unit.
2.1. ERROR DETECTION 35 2.1.3 Information Redundancy The basic idea behind an information scheme is to add redundant information to the data being transmitted or stored or processed to determine if errors have been introduced [IK03]. It is the way of protecting data through mathematical encoding, which can be reuse after decode the original data (as in figure 2.5). The encoding and decoding circuitry adds additional delays, which make them slower than DMR, but the area overhead is much lower than DMR. In coding, the consideration is given to the information stored or maybe to the functionality of the circuit but no consideration given to the structure of the circuit. Typically, information redundancy is used to protect storage elements (like memory, caches, register files, etc) [HCTS10] e.g. in Power 6 and 7 [KMSK09]. These codes are classified based on their ability of detection and correction, code efficiency and complexity. In this section, we will discuss only error detection codes. Data Encode Add Redundancy Noise Transmit or Store Decode Data Check Redundancy Figure 2.5: Information redundancy principle The error detecting codes (EDC) have less hardware overhead than the error correcting codes. There are different EDCs e.g. parity, Borden, Berger and Bose codes. We will not go in much details but will compare their salient features will be discussed. The parity-coding strategies is simplest and it has lowest HW overhead [ARM + 11]. It is based on calculation of even or odd parity for data of word length N. The parity can be calculated with XOR operation among the data bit. A parity code has a distance of 2 and can detect all odd-bit errors. Input Parity Generator P Data Data Received data comparator Figure 2.6: Parity coder in data storage Error Signal Output Before storing data in the register, the parity generator is used to compute the parity bit required (as shown in the figure 2.6). Then both the computed parity and the original data are stored in register.
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 8 and 9: 2 CONTENTS 2.3 Error Recovery . . .
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13 and 14: General Introduction owadays, devic
Page 15 and 16: checking processor core (SCPC). The
Page 17: I. STATE OF ART 11
Page 20 and 21: 14 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
Page 59 and 60: Chapter 3 Design Methodology and Mo
Page 61 and 62: 3.2. METHODOLOGY 55 further investi
Page 63 and 64: 3.2. METHODOLOGY 57 software techni
Page 65 and 66: 3.5. DESIGN CHALLENGES 59 3.5 Desig
Page 67 and 68: 3.5. DESIGN CHALLENGES 61 Self-Chec
Page 69 and 70: 3.6. MODEL SPECIFICATIONS AND GLOBA
Page 71 and 72: 3.7. FUNCTIONAL IMPLEMENTATION 65 (
Page 73 and 74: 3.7. FUNCTIONAL IMPLEMENTATION 67 n
Page 75 and 76: 3.7. FUNCTIONAL IMPLEMENTATION 69 C
Page 77 and 78: 3.7. FUNCTIONAL IMPLEMENTATION 71 C
Page 79 and 80: 3.8. CONCLUSIONS 73 Free space Data
Page 81 and 82: 3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
Page 83 and 84: Chapter 4 Design and Implementation
Page 85 and 86: 4.1. PROCESSOR DESIGN STRATEGY 79 F
Page 87 and 88: 4.2. PROPOSED ARCHITECTURE 81 2 Num
Page 89 and 90: 4.3. HARDWARE MODEL OF THE STACK PR
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4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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