Dependable Memory - Laboratoire Interface Capteurs ...

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24 CHAPTER 1. DEPENDABILITY AND FAULT TOLERANCE Sr. No. 1 2 3 4 5 6 7 Nature Fault at different level Specification Mistakes Programming fault HDL Component defect 1 Component defect 2 External Disturbance Fault due to lower noise Correct state A B C if a < = b c : c + 1; end; r1 : c
1.5. MEANS 25 Extent A permanent fault if occurs once, persists until the end of the execution. Even a single permanent fault can create multiple errors until being repaired. Such errors are called hard errors. • Intermittent: It is a fault which appears, disappears, and reappears repeatedly within a very short period. An intermittent fault can occur repeatedly but not continuously for a long time in a device. The errors in modern computers may result due to permanent, intermediate and transient faults. However, transient faults occur considerably more often than permanent ones, and are much harder to detect [RS09]. The ratios of transient-to-permanent faults can vary between 2:1, 100:1 or higher. This ratio is continuously increasing [Kop04]. The fault extent specifies whether the fault is localized to a given hardware or software module or whether it globally affects the hardware, the software, or both. Value The fault value can either be determinate or indeterminate. A determinate fault is one whose status remain unchanged throughout the time unless there is an external action upon it, whereas an indeterminate fault is one whose status at some time t may be different from its status at another time. 1.5 Means There are four means to attain dependability: fault prevention, fault tolerance, fault removal and fault forecasting. Fault prevention and fault tolerance aim to provide the ability to deliver a service that can be trusted, while fault removal and fault forecasting aim to reach confidence in that ability by justifying that the functional and the dependability and security specifications are adequate and that the system is likely to meet them [LRL04, LB07]. 1.5.1 Fault Prevention Fault prevention is the ability to avoid the occurrence or introduction of the faults. Fault prevention includes any technique that attempts to prevent the occurrence of faults. It can include design reviews, component screening, testing and other quality control methods. 1.5.2 Fault Removal Fault removal is the ability to lessen the number and severity of faults. It can be conducted during corrective or preventive maintenance processes. Corrective maintenance aims to remove faults
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 8 and 9: 2 CONTENTS 2.3 Error Recovery . . .
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13 and 14: General Introduction owadays, devic
Page 15 and 16: checking processor core (SCPC). The
Page 17: I. STATE OF ART 11
Page 20 and 21: 14 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
Page 59 and 60: Chapter 3 Design Methodology and Mo
Page 61 and 62: 3.2. METHODOLOGY 55 further investi
Page 63 and 64: 3.2. METHODOLOGY 57 software techni
Page 65 and 66: 3.5. DESIGN CHALLENGES 59 3.5 Desig
Page 67 and 68: 3.5. DESIGN CHALLENGES 61 Self-Chec
Page 69 and 70: 3.6. MODEL SPECIFICATIONS AND GLOBA
Page 71 and 72: 3.7. FUNCTIONAL IMPLEMENTATION 65 (
Page 73 and 74: 3.7. FUNCTIONAL IMPLEMENTATION 67 n
Page 75 and 76: 3.7. FUNCTIONAL IMPLEMENTATION 69 C
Page 77 and 78: 3.7. FUNCTIONAL IMPLEMENTATION 71 C
Page 79 and 80: 3.8. CONCLUSIONS 73 Free space Data
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3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
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Chapter 4 Design and Implementation
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4.1. PROCESSOR DESIGN STRATEGY 79 F
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4.2. PROPOSED ARCHITECTURE 81 2 Num
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4.3. HARDWARE MODEL OF THE STACK PR
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4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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