Dependable Memory - Laboratoire Interface Capteurs ...

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14 CHAPTER 1. DEPENDABILITY AND FAULT TOLERANCE trends that increase the probability of faults and the sources and consequences of the faults. The second part discusses the concepts of dependable computing and third part will be exploring the means to attain dependability. 1.1 Problematic For many years researchers focused on performance issues. Due to their restless effort, they have improved the overall performance in last few years fueled by deep technology scaling. However, the boundaries provided by the Moore’s law have been reached to its saturation level and on the other hand; there is a decrease in the dependability due to ever-increasing physical faults. There are various trends in search of high performance, which have increased the need for dependable architecture design. Among them, some are discussed below: Smaller Technologies / Design Scales Although scaling of the transistors and wires has steadily improved processor performance and reduced cost, it also adversely affected long-term chip lifetime reliability. When a transistor is ex- posed to high-energy ionizing radiation, electron-hole pairs are created [SSF + 08]. Transistor source and diffusion nodes accumulate charge, which may invert the logic state of the transistor [Muk08]. With device dimensions projected to shrink below 18 nanometers by 2015 significantly threaten next- generation technologies [RYKO11]. For transient faults, smaller devices tend to have low charge to hold the states of the registers and make them more sensitive towards noise. When the noise margin decreases the probability that a high-energy particle strike can disturb the charge on the devices also increases which in turn increases the probability of transient faults. The lower voltages used for power efficiency reasons will increase the susceptibility of future chips [FGAD10]. More Transistors per Chip Due to more transistors, more wires are required to connect them, resulting in more chances of faults both during the fabrication and working of such devices. Modern processors are more prone to the faults due to greater number of transistors and registers. Moreover, temperature is another factor causing transient and permanent faults. More the devices on the chip so more power will be dragged from the supply. Higher supply power per unit area will increase the leakage power dissipated per unit area due to which higher will be the temperature and probability of errors. Complex Design Today, the processor has become more complicated as compared to the past, which increases the probability of design faults. On the other hand it is also making debugging of errors difficult. Research effort is oriented towards alternate methods to increase system performance without increasing the
1.1. PROBLEMATIC 15 sensitivity of the circuit but unfortunately the bottleneck has been reached and alternate solutions are more complex and make fault debugging a more difficult task to fulfill. In short, the devices are becoming more sensitive against ionized radiation (which may cause soft errors), operating point variation by means of temperature or supply voltage fluctuations, as well as parasitic effects, which results in statical leakage currents [ITR07]. Changing the parameters like dimensions, noise margin and supplied voltage cannot be further fruitful to increase the performance. In the near future, due to small size and high frequency the failure trend in modern computing systems will further increase because saturation level has already been reached. The further increase is leading towards increasing rate of soft error in logic and memory chips [Bau05] which is affecting the reliability even at sea level [WA08]. To assure the circuit integrity, FT must be an important design consideration for modern circuits. The dependable system must be aware of the tolerance mechanism against possible errors. 1.1.1 Common Source of Faults and their Consequences Today, one significant threat to the reliability of the digital circuits is concerned with the sensitivity of the logic states to various noise sources and specially in certain specific environments such as in space or nuclear systems where collision of charged particles can result in transient faults. Such particles may include cosmic rays produced by sun and alpha particles produced by disintegration of radioactive isotopes. For space applications, FT is a mandatory requirement due to the severe radiation environment. As the manufacturing technology is scaled towards finer geometries the probability for SEUs is increasing. With the present technology, dependability is not only required for some critical applications: even for commodity systems, dependability needs to be above a certain level for the system to be useful for anything [FGAD10]. Radiation induced soft error is becoming an increasingly important threat to the reliability of digital circuits even in ground level applications [Nic10]. Transient faults can be caused by on-chip perturbations, like power supply noise or external noise [NX06]. The researchers have classified three common sources of soft errors in semi-conductors including alpha particles, discovered in 1970’s, proved to be the main source of soft errors in computer systems, specially DRAM [MW07]. Secondly, the high-energy neutrons from cosmic radia- tions could induce soft errors in semi conductor devices via the secondary ions produced by neutron reaction with silicon nuclei [ZL09] as shown in figure 1.1, where a single high-energy neutron has disturbed the internal charge distribution of the whole device. Thirdly, soft-error source is induced by low-energy cosmic neutron interactions with the isotope boron-10 in IC materials, specifically in Boro-Phos-Silicate-Glass (BPSG), used widely to form insulator layers in IC manufacturing. This recently proved to be the dominant source of soft errors in SRAM fabricated with BPSG [WA08]. Figure 1.2 represents the sequence of events that may occur once an energetic particle hit the substrate provoking ionization. This ionization may generates a set of electron-hole pairs that create a transient current that is injected or extracted to that node. According to the amplitude and duration
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 8 and 9: 2 CONTENTS 2.3 Error Recovery . . .
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13 and 14: General Introduction owadays, devic
Page 15 and 16: checking processor core (SCPC). The
Page 17: I. STATE OF ART 11
Page 22 and 23: 16 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
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Page 61 and 62: 3.2. METHODOLOGY 55 further investi
Page 63 and 64: 3.2. METHODOLOGY 57 software techni
Page 65 and 66: 3.5. DESIGN CHALLENGES 59 3.5 Desig
Page 67 and 68: 3.5. DESIGN CHALLENGES 61 Self-Chec
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3.7. FUNCTIONAL IMPLEMENTATION 65 (
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3.7. FUNCTIONAL IMPLEMENTATION 67 n
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3.7. FUNCTIONAL IMPLEMENTATION 69 C
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3.7. FUNCTIONAL IMPLEMENTATION 71 C
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3.8. CONCLUSIONS 73 Free space Data
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3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
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Chapter 4 Design and Implementation
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4.1. PROCESSOR DESIGN STRATEGY 79 F
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4.2. PROPOSED ARCHITECTURE 81 2 Num
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4.3. HARDWARE MODEL OF THE STACK PR
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4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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