Dependable Memory - Laboratoire Interface Capteurs ...

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20 CHAPTER 1. DEPENDABILITY AND FAULT TOLERANCE sometimes one overlooks maintenance and the safety decreases accordingly. Here, two types of systems have been considered: • a web server • a nuclear reactors Let us see which dependability and security attributes are more important for each of the system. In a university web-server, availability is the important attribute because every student needs to ac- cess it regularly whereas, for a nuclear reactor, the attributes like availability, reliability, safety and maintainability are important considerations. The [Pie07] sum up the importance of these attributes inform of a table in 1.2, where 4 points have been given to very important attributes and 1 to least important attribute. Hence from the table 1.2 each application has its only dependability and security requirements. Table 1.2: Dependability attributes for University web-server and Nuclear-reactor [Pie07], where attributes are classified as: – very important = 4 points, – least important = 1 point 1.4 Threats Attributes University Web Server Nuclear Reactor Availability 3 4 Reliability 1 4 Safety 1 4 confidentiality 2 1 Integrity 2 3 Maintainability 2 4 There are three fundamental threats to a dependable computer. They are: (i) fault, (ii) error and (iii) failures. Fault is define as an erroneous state of hardware or software resulting from failures of components, physical interference from the environment, operator error, or incorrect design [Pie06]. A fault is active when it produces an error, otherwise it is considered as a dormant/sleeping fault. An active fault can be an internal fault that was previously dormant. The error is itself caused by a fault and a failure occurs when there is deviation from correct services due to some error. All three have cause and affect relationship between them (as shown in figure 1.5). In general, active fault causes error. It can propagate from one place to another inside the system. In figure 1.6, an error produced in the processor has been transfered to main memory. Furthermore, if an error reaches the boundaries of the system it may result in the failure of the system, causing the service provided to deviate from its specification [GMT08] (see figure 1.5). If the initial system is a sub-system of a global system then it can cause a fault in the global system. In this way chain of fault, error and failure keep on progressing.
1.4. THREATS 21 Sub-system Global system ….. Fault Error Failure Fault Error ….. Activation Propagation Consequences Activation activation Figure 1.5: Fault, error and failure chain propagation propagation fault error error error Processor Main <strong>Memory</strong> READ/ WRITE Figure 1.6: Error propagation from processor to main memory A SEU may result in system failure, like in figure 1.7: a high-energy neutron strike (caused due to cosmic rays) on a VLSI circuit has resulted into a SBU (active fault), which provoked an error in traffic control system and finally resulted into the system failure. 1.4.1 System Failure A correct service is given by a system when it is respecting its functionality. Whereas, a system failure is a deviation of the service delivered by the system from its specification [Pie06]. Such a deviation can be in the form of incorrect service, or no service at all [GMT08]. Whereas, the transition from incorrect to correct service is a service restoration (see figure 1.8). The service failure may occur because the system is no more respecting its functionality or maybe the functional specifications were not correctly defined for that system under certain conditions. On the other hand, FT techniques allow a system to continuously deliver its service according to its correct functionality even in the presence of faults.
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 8 and 9: 2 CONTENTS 2.3 Error Recovery . . .
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13 and 14: General Introduction owadays, devic
Page 15 and 16: checking processor core (SCPC). The
Page 17: I. STATE OF ART 11
Page 20 and 21: 14 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
Page 59 and 60: Chapter 3 Design Methodology and Mo
Page 61 and 62: 3.2. METHODOLOGY 55 further investi
Page 63 and 64: 3.2. METHODOLOGY 57 software techni
Page 65 and 66: 3.5. DESIGN CHALLENGES 59 3.5 Desig
Page 67 and 68: 3.5. DESIGN CHALLENGES 61 Self-Chec
Page 69 and 70: 3.6. MODEL SPECIFICATIONS AND GLOBA
Page 71 and 72: 3.7. FUNCTIONAL IMPLEMENTATION 65 (
Page 73 and 74: 3.7. FUNCTIONAL IMPLEMENTATION 67 n
Page 75 and 76: 3.7. FUNCTIONAL IMPLEMENTATION 69 C
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3.7. FUNCTIONAL IMPLEMENTATION 71 C
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3.8. CONCLUSIONS 73 Free space Data
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3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
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Chapter 4 Design and Implementation
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4.1. PROCESSOR DESIGN STRATEGY 79 F
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4.2. PROPOSED ARCHITECTURE 81 2 Num
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4.3. HARDWARE MODEL OF THE STACK PR
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4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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