Dependable Memory - Laboratoire Interface Capteurs ...

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2 CONTENTS 2.3 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4 FT Processor Design Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5 FT Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.5.1 Fault Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.5.2 Error Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.5.3 The Fault Injection Framework . . . . . . . . . . . . . . . . . . . . . . . . 48 2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 II. QUALITATIVE AND QUANTITATIVE STUDY 53 3 Design Methodology and Model Specifications 53 3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.1 Concurrent Error Detection: Parity Codes . . . . . . . . . . . . . . . . . . . 54 3.2.2 Error Recovery: Rollback . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4 Hypothesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.5 Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.5.1 Challenge # 1: Self Checking Processor Core Requirements . . . . . . . . . 59 3.5.2 Challenge # 2: Temporary Storage Needed: Hardware Journal . . . . . . . . 60 3.5.3 Challenge # 3: Processor-<strong>Memory</strong> Interfacing . . . . . . . . . . . . . . . . . 62 3.5.4 Challenge # 4: Optimal Sequence Duration for Efficient Implementation of Rollback Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.6 Model Specifications and Global Design Flow . . . . . . . . . . . . . . . . . . . . . 63 3.7 Functional Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.7.1 Model-I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.7.2 Model-II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.7.3 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4 Design and Implementation of a Self Checking Processor 77 4.1 Processor Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.1.1 Advantages of Stack Processor . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.3 Hardware Model of the Stack Processor . . . . . . . . . . . . . . . . . . . . . . . . 82 4.4 Design Challenges in FT Stack Processor . . . . . . . . . . . . . . . . . . . . . . . 84 4.4.1 Challenge I: Self Checking Mechanism . . . . . . . . . . . . . . . . . . . . 85 4.4.2 Challenge II: Performance Improvement . . . . . . . . . . . . . . . . . . . . 85 4.5 Solution-I: Self Checking Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . 87
CONTENTS 3 4.5.1 Error Detecting in ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.5.2 Error Detecting in Register and Data-Path . . . . . . . . . . . . . . . . . . . 92 4.5.3 Self-Checking Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.5.4 Store Sensitive Elements (SE) . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.5.5 Protecting Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.6 Solution-II: Performance Aspects of Self-Checking Processor Core . . . . . . . . . . 94 4.6.1 Solution-II (a): Multiple-byte Instructions . . . . . . . . . . . . . . . . . . . 94 4.6.2 Solution-II (b): 2-Stage Pipelining to resolve Multi-clock Instruction Execution 95 4.6.3 Reducing Overhead for Conditional Branches . . . . . . . . . . . . . . . . . 96 4.7 Implementation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5 Design of a Self Checking Hardware Journal 103 5.1 Error Detection and Correction in the Journal . . . . . . . . . . . . . . . . . . . . . 104 5.2 Principle of the technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3 Journal Architecture and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.3.1 Modes of SCHJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.4 Risk of data contamination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.5 Implementation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.5.1 Minimizing the Size of the Journal . . . . . . . . . . . . . . . . . . . . . . . 115 5.5.2 Dynamic Sequence Duration . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6 Fault Tolerant Processor Validation 121 6.1 Design Hypothesis and Properties to be Checked . . . . . . . . . . . . . . . . . . . 122 6.2 Error Injection Methodology and Error Profiles . . . . . . . . . . . . . . . . . . . . 122 6.3 Experimental Validation of Self-Checking Methodology . . . . . . . . . . . . . . . 123 6.4 Performance Degradation due to Re-execution . . . . . . . . . . . . . . . . . . . . . 126 6.4.1 Evaluating Performance Degradation . . . . . . . . . . . . . . . . . . . . . 127 6.5 Effect of Error Injection on Rate of Rollback . . . . . . . . . . . . . . . . . . . . . . 130 6.6 Comparison with LEON FT-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 GENERAL CONCLUSION AND PROSPECTS 135 A Canonical Stack Computers: 139 B Instruction Set of Stack Processor 141 B.1 Data Operations in Stack Processor: . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Page 1: LABORATOIRE INTERFACES CAPTEURS ET
Page 5: Acknowledgements A PhD thesis is a
Page 10 and 11: 4 CONTENTS C Instruction Set of Pip
Page 13 and 14: General Introduction owadays, devic
Page 15 and 16: checking processor core (SCPC). The
Page 17: I. STATE OF ART 11
Page 20 and 21: 14 CHAPTER 1. DEPENDABILITY AND FAU
Page 38 and 39: 32 CHAPTER 2. METHODS TO DESIGN AND
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Chapter 3 Design Methodology and Mo
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3.2. METHODOLOGY 55 further investi
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3.2. METHODOLOGY 57 software techni
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3.5. DESIGN CHALLENGES 59 3.5 Desig
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3.5. DESIGN CHALLENGES 61 Self-Chec
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3.6. MODEL SPECIFICATIONS AND GLOBA
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3.7. FUNCTIONAL IMPLEMENTATION 65 (
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3.7. FUNCTIONAL IMPLEMENTATION 67 n
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3.7. FUNCTIONAL IMPLEMENTATION 69 C
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3.7. FUNCTIONAL IMPLEMENTATION 71 C
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3.8. CONCLUSIONS 73 Free space Data
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3.8. CONCLUSIONS 75 CPI*/CPI 4 3.5
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Chapter 4 Design and Implementation
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4.1. PROCESSOR DESIGN STRATEGY 79 F
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4.2. PROPOSED ARCHITECTURE 81 2 Num
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4.3. HARDWARE MODEL OF THE STACK PR
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4.4. DESIGN CHALLENGES IN FT STACK
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4.5. SOLUTION-I: SELF CHECKING MECH
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.6. SOLUTION-II: PERFORMANCE ASPEC
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4.7. IMPLEMENTATION RESULTS 99 LSB
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4.8. CONCLUSIONS 101 In the next ch
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Chapter 5 Design of a Self Checking
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5.2. PRINCIPLE OF THE TECHNIQUE 105
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5.3. JOURNAL ARCHITECTURE AND OPERA
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5.4. RISK OF DATA CONTAMINATION 113
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5.5. IMPLEMENTATION RESULTS 115 Err
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5.5. IMPLEMENTATION RESULTS 117 (a)
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5.6. CONCLUSIONS 119 5.5.2 Dynamic
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Chapter 6 Fault Tolerant Processor
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.3. EXPERIMENTAL VALIDATION OF SEL
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.4. PERFORMANCE DEGRADATION DUE TO
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6.6. COMPARISON WITH LEON FT-3 131
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GENERAL CONCLUSION AND PROSPECTS 13
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136 GENERAL CONCLUSIONS amount of h
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Appendix A Canonical Stack Computer
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Appendix B Instruction Set of Stack
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Table B.2: Stack manipulation opera
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B.1. DATA OPERATIONS IN STACK PROCE
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Appendix C Instruction Set of Pipel
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Table C.2: Stack manipulation opera
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Table C.8: Instruction Codes and In
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Appendix D List of Acronyms ALU : A
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SoC : System on Chip. STAR : Self-T
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Appendix E List of publications •
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List of Figures 1.1 An alpha partic
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LIST OF FIGURES 161 4.15 Parity che
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List of Tables 1.1 Cost/hour for fa
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Bibliography [ACC + 93] J. Arlat, A
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BIBLIOGRAPHY 167 [EAWJ02] E. N. Eln
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BIBLIOGRAPHY 169 [KKS + 07] P. Kudv
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BIBLIOGRAPHY 171 [NMGT06] J. Nakano
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BIBLIOGRAPHY 173 [SMHW02] D. J Sori
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RÉSUMÉ Dans cette thèse, nous pr
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